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Merge pull request #3103 from whitequark/write_verilog-more-zero-width-values 

write_verilog: dump zero width sigspecs correctly
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Catherine 2021-12-11 16:24:47 +00:00 committed by GitHub
parent 8e91857fab 86f2804dc3
commit 21fbdb6638
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1 changed files with 2 additions and 1 deletions
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3
backends/verilog/verilog_backend.cc
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@ -358,7 +358,8 @@ void dump_sigchunk(std::ostream &f, const RTLIL::SigChunk &chunk, bool no_decima
void dump_sigspec(std::ostream &f, const RTLIL::SigSpec &sig)
{
if (GetSize(sig) == 0) {
f << "\"\"";
// See IEEE 1364-2005 Clause 5.1.14.
f << "{0{1'b0}}";
return;
}
if (sig.is_chunk()) {