riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Merge pull request #3103 from whitequark/write_verilog-more-zero-width-values 

write_verilog: dump zero width sigspecs correctly
This commit is contained in:
Catherine 2021-12-11 16:24:47 +00:00 committed by GitHub
parent 8e91857fab 86f2804dc3
commit 21fbdb6638
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 2 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
backends/verilog/verilog_backend.cc
View File

@ -358,7 +358,8 @@ void dump_sigchunk(std::ostream &f, const RTLIL::SigChunk &chunk, bool no_decima
void dump_sigspec(std::ostream &f, const RTLIL::SigSpec &sig) void dump_sigspec(std::ostream &f, const RTLIL::SigSpec &sig)
{ {
if (GetSize(sig) == 0) { if (GetSize(sig) == 0) {
f << "\"\""; // See IEEE 1364-2005 Clause 5.1.14.
f << "{0{1'b0}}";
return; return;
} }
if (sig.is_chunk()) { if (sig.is_chunk()) {