From 20d864bbdeee0b7854e5a6816159a12b21cb4861 Mon Sep 17 00:00:00 2001 From: "N. Engelhardt" Date: Mon, 27 Nov 2023 10:35:29 +0100 Subject: [PATCH] add dsp inference --- techlibs/quicklogic/.gitignore | 1 + techlibs/quicklogic/Makefile.inc | 23 +- .../{ql-bram-merge.cc => ql_bram_merge.cc} | 0 .../{ql-bram-types.cc => ql_bram_types.cc} | 0 techlibs/quicklogic/ql_dsp_io_regs.cc | 244 + techlibs/quicklogic/ql_dsp_macc.cc | 307 + techlibs/quicklogic/ql_dsp_macc.pmg | 50 + techlibs/quicklogic/ql_dsp_simd.cc | 359 + .../quicklogic/qlf_k6n10f/dsp_final_map.v | 265 + techlibs/quicklogic/qlf_k6n10f/dsp_map.v | 147 + techlibs/quicklogic/qlf_k6n10f/dsp_sim.v | 5753 +++++++++++++++++ techlibs/quicklogic/synth_quicklogic.cc | 47 +- 12 files changed, 7189 insertions(+), 7 deletions(-) create mode 100644 techlibs/quicklogic/.gitignore rename techlibs/quicklogic/{ql-bram-merge.cc => ql_bram_merge.cc} (100%) rename techlibs/quicklogic/{ql-bram-types.cc => ql_bram_types.cc} (100%) create mode 100644 techlibs/quicklogic/ql_dsp_io_regs.cc create mode 100644 techlibs/quicklogic/ql_dsp_macc.cc create mode 100644 techlibs/quicklogic/ql_dsp_macc.pmg create mode 100644 techlibs/quicklogic/ql_dsp_simd.cc create mode 100644 techlibs/quicklogic/qlf_k6n10f/dsp_final_map.v create mode 100644 techlibs/quicklogic/qlf_k6n10f/dsp_map.v create mode 100644 techlibs/quicklogic/qlf_k6n10f/dsp_sim.v diff --git a/techlibs/quicklogic/.gitignore b/techlibs/quicklogic/.gitignore new file mode 100644 index 000000000..e52f3282f --- /dev/null +++ b/techlibs/quicklogic/.gitignore @@ -0,0 +1 @@ +/*_pm.h diff --git a/techlibs/quicklogic/Makefile.inc b/techlibs/quicklogic/Makefile.inc index df69a3fc3..ce5ff859b 100644 --- a/techlibs/quicklogic/Makefile.inc +++ b/techlibs/quicklogic/Makefile.inc @@ -1,6 +1,20 @@ +%_pm.h: passes/pmgen/pmgen.py %.pmg + $(P) mkdir -p pmgen && $(PYTHON_EXECUTABLE) $< -o $@ -p $(subst _pm.h,,$(notdir $@)) $(filter-out $<,$^) + OBJS += techlibs/quicklogic/synth_quicklogic.o -OBJS += techlibs/quicklogic/ql-bram-merge.o -OBJS += techlibs/quicklogic/ql-bram-types.o +OBJS += techlibs/quicklogic/ql_bram_merge.o +OBJS += techlibs/quicklogic/ql_bram_types.o +OBJS += techlibs/quicklogic/ql_dsp_simd.o +OBJS += techlibs/quicklogic/ql_dsp_io_regs.o + +# -------------------------------------- + +OBJS += techlibs/quicklogic/ql_dsp_macc.o +GENFILES += techlibs/quicklogic/ql_dsp_macc_pm.h +techlibs/quicklogic/ql_dsp_macc.o: techlibs/quicklogic/ql_dsp_macc_pm.h +$(eval $(call add_extra_objs,techlibs/quicklogic/ql_dsp_macc_pm.h)) + +# -------------------------------------- $(eval $(call add_share_file,share/quicklogic/common,techlibs/quicklogic/common/cells_sim.v)) @@ -21,4 +35,7 @@ $(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf $(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/brams_sim.v)) $(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/bram_types_sim.v)) $(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/cells_sim.v)) -$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/ffs_map.v)) \ No newline at end of file +$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/ffs_map.v)) +$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/dsp_sim.v)) +$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/dsp_map.v)) +$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/dsp_final_map.v)) \ No newline at end of file diff --git a/techlibs/quicklogic/ql-bram-merge.cc b/techlibs/quicklogic/ql_bram_merge.cc similarity index 100% rename from techlibs/quicklogic/ql-bram-merge.cc rename to techlibs/quicklogic/ql_bram_merge.cc diff --git a/techlibs/quicklogic/ql-bram-types.cc b/techlibs/quicklogic/ql_bram_types.cc similarity index 100% rename from techlibs/quicklogic/ql-bram-types.cc rename to techlibs/quicklogic/ql_bram_types.cc diff --git a/techlibs/quicklogic/ql_dsp_io_regs.cc b/techlibs/quicklogic/ql_dsp_io_regs.cc new file mode 100644 index 000000000..217a5aa55 --- /dev/null +++ b/techlibs/quicklogic/ql_dsp_io_regs.cc @@ -0,0 +1,244 @@ +/* + * Copyright 2020-2022 F4PGA Authors + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * SPDX-License-Identifier: Apache-2.0 + * + */ + +#include "kernel/sigtools.h" +#include "kernel/yosys.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +#define MODE_BITS_REGISTER_INPUTS_ID 92 +#define MODE_BITS_OUTPUT_SELECT_START_ID 81 +#define MODE_BITS_OUTPUT_SELECT_WIDTH 3 + +// ============================================================================ + +struct QlDspIORegs : public Pass { + + const std::vector ports2del_mult = {"load_acc", "subtract", "acc_fir", "dly_b"}; + const std::vector ports2del_mult_acc = {"acc_fir", "dly_b"}; + const std::vector ports2del_mult_add = {"dly_b"}; + const std::vector ports2del_extension = {"saturate_enable", "shift_right", "round"}; + + /// Temporary SigBit to SigBit helper map. + SigMap m_SigMap; + + // .......................................... + + QlDspIORegs() : Pass("ql_dsp_io_regs", "Changes types of QL_DSP2/QL_DSP3 depending on their configuration.") {} + + void help() override + { + log("\n"); + log(" ql_dsp_io_regs [options] [selection]\n"); + log("\n"); + log("Looks for QL_DSP2/QL_DSP3 cells and changes their types depending\n"); + log("on their configuration.\n"); + } + + void execute(std::vector a_Args, RTLIL::Design *a_Design) override + { + log_header(a_Design, "Executing QL_DSP_IO_REGS pass.\n"); + + size_t argidx; + for (argidx = 1; argidx < a_Args.size(); argidx++) { + break; + } + extra_args(a_Args, argidx, a_Design); + + for (auto module : a_Design->selected_modules()) { + ql_dsp_io_regs_pass(module); + } + } + + // Returns a pair of mask and value describing constant bit connections of + // a SigSpec + std::pair get_constant_mask_value(const RTLIL::SigSpec *sigspec) + { + uint32_t mask = 0L; + uint32_t value = 0L; + + auto sigbits = sigspec->bits(); + for (ssize_t i = (sigbits.size() - 1); i >= 0; --i) { + auto other = m_SigMap(sigbits[i]); + + mask <<= 1; + value <<= 1; + + // A known constant + if (!other.is_wire() && other.data != RTLIL::Sx) { + mask |= 0x1; + value |= (other.data == RTLIL::S1); + } + } + + return std::make_pair(mask, value); + } + + void ql_dsp_io_regs_pass(RTLIL::Module *module) + { + // Setup the SigMap + m_SigMap.clear(); + m_SigMap.set(module); + + for (auto cell : module->cells_) { + std::string cell_type = cell.second->type.str(); + if (cell_type == RTLIL::escape_id("QL_DSP2") || cell_type == RTLIL::escape_id("QL_DSP3")) { + auto dsp = cell.second; + + // If the cell does not have the "is_inferred" attribute set + // then don't touch it. + if (!dsp->has_attribute(RTLIL::escape_id("is_inferred")) || dsp->get_bool_attribute(RTLIL::escape_id("is_inferred")) == false) { + continue; + } + + bool del_clk = true; + bool use_dsp_cfg_params = (cell_type == RTLIL::escape_id("QL_DSP3")); + + int reg_in_i; + int out_sel_i; + + // Get DSP configuration + if (use_dsp_cfg_params) { + // Read MODE_BITS at correct indexes + auto mode_bits = &dsp->getParam(RTLIL::escape_id("MODE_BITS")); + RTLIL::Const register_inputs; + register_inputs = mode_bits->bits.at(MODE_BITS_REGISTER_INPUTS_ID); + reg_in_i = register_inputs.as_int(); + + RTLIL::Const output_select; + output_select = mode_bits->extract(MODE_BITS_OUTPUT_SELECT_START_ID, MODE_BITS_OUTPUT_SELECT_WIDTH); + out_sel_i = output_select.as_int(); + } else { + // Read dedicated configuration ports + const RTLIL::SigSpec *register_inputs; + register_inputs = &dsp->getPort(RTLIL::escape_id("register_inputs")); + if (!register_inputs) + log_error("register_inputs port not found!"); + auto reg_in_c = register_inputs->as_const(); + reg_in_i = reg_in_c.as_int(); + + const RTLIL::SigSpec *output_select; + output_select = &dsp->getPort(RTLIL::escape_id("output_select")); + if (!output_select) + log_error("output_select port not found!"); + auto out_sel_c = output_select->as_const(); + out_sel_i = out_sel_c.as_int(); + } + + // Get the feedback port + const RTLIL::SigSpec *feedback; + feedback = &dsp->getPort(RTLIL::escape_id("feedback")); + if (!feedback) + log_error("feedback port not found!"); + + // Check if feedback is or can be set to 0 which implies MACC + auto feedback_con = get_constant_mask_value(feedback); + bool have_macc = (feedback_con.second == 0x0); + // log("mask=0x%08X value=0x%08X\n", consts.first, consts.second); + // log_error("=== END HERE ===\n"); + + // Build new type name + std::string new_type = cell_type; + new_type += "_MULT"; + + if (have_macc) { + switch (out_sel_i) { + case 1: + case 2: + case 3: + case 5: + case 7: + del_clk = false; + new_type += "ACC"; + break; + default: + break; + } + } else { + switch (out_sel_i) { + case 1: + case 2: + case 3: + case 5: + case 7: + new_type += "ADD"; + break; + default: + break; + } + } + + if (reg_in_i) { + del_clk = false; + new_type += "_REGIN"; + } + + if (out_sel_i > 3) { + del_clk = false; + new_type += "_REGOUT"; + } + + // Set new type name + dsp->type = RTLIL::IdString(new_type); + + std::vector ports2del; + + if (del_clk) + ports2del.push_back("clk"); + + switch (out_sel_i) { + case 0: + case 4: + case 6: + ports2del.insert(ports2del.end(), ports2del_mult.begin(), ports2del_mult.end()); + // Mark for deleton additional configuration ports + if (!use_dsp_cfg_params) { + ports2del.insert(ports2del.end(), ports2del_extension.begin(), ports2del_extension.end()); + } + break; + case 1: + case 2: + case 3: + case 5: + case 7: + if (have_macc) { + ports2del.insert(ports2del.end(), ports2del_mult_acc.begin(), ports2del_mult_acc.end()); + } else { + ports2del.insert(ports2del.end(), ports2del_mult_add.begin(), ports2del_mult_add.end()); + } + break; + } + + for (auto portname : ports2del) { + const RTLIL::SigSpec *port = &dsp->getPort(RTLIL::escape_id(portname)); + if (!port) + log_error("%s port not found!", portname.c_str()); + dsp->connections_.erase(RTLIL::escape_id(portname)); + } + } + } + + // Clear the sigmap + m_SigMap.clear(); + } + +} QlDspIORegs; + +PRIVATE_NAMESPACE_END diff --git a/techlibs/quicklogic/ql_dsp_macc.cc b/techlibs/quicklogic/ql_dsp_macc.cc new file mode 100644 index 000000000..ca898d9d0 --- /dev/null +++ b/techlibs/quicklogic/ql_dsp_macc.cc @@ -0,0 +1,307 @@ +/* + * Copyright 2020-2022 F4PGA Authors + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * SPDX-License-Identifier: Apache-2.0 + * + */ + +#include "kernel/sigtools.h" +#include "kernel/yosys.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +#include "ql_dsp_macc_pm.h" + +// ============================================================================ + +bool use_dsp_cfg_params; + +static void create_ql_macc_dsp(ql_dsp_macc_pm &pm) +{ + auto &st = pm.st_ql_dsp_macc; + + // Reject if multiplier drives anything else than either $add or $add and + // $mux + if (st.mux == nullptr && st.mul_nusers > 2) { + return; + } + + // Determine whether the output is taken from before or after the ff + bool out_ff; + if (st.ff_d_nusers == 2 && st.ff_q_nusers == 3) { + out_ff = true; + } else if (st.ff_d_nusers == 3 && st.ff_q_nusers == 2) { + out_ff = false; + } else { + // Illegal, cannot take the two outputs simulataneously + return; + } + + // No mux, the adder can driver either the ff or the ff + output + if (st.mux == nullptr) { + if (out_ff && st.add_nusers != 2) { + return; + } + if (!out_ff && st.add_nusers != 3) { + return; + } + } + // Mux present, the adder cannot drive anything else + else { + if (st.add_nusers != 2) { + return; + } + } + + // Mux can driver either the ff or the ff + output + if (st.mux != nullptr) { + if (out_ff && st.mux_nusers != 2) { + return; + } + if (!out_ff && st.mux_nusers != 3) { + return; + } + } + + // Accept only posedge clocked FFs + if (st.ff->getParam(ID(CLK_POLARITY)).as_int() != 1) { + return; + } + + // Get port widths + size_t a_width = GetSize(st.mul->getPort(ID(A))); + size_t b_width = GetSize(st.mul->getPort(ID(B))); + size_t z_width = GetSize(st.ff->getPort(ID(Q))); + + size_t min_width = std::min(a_width, b_width); + size_t max_width = std::max(a_width, b_width); + + // Signed / unsigned + bool a_signed = st.mul->getParam(ID(A_SIGNED)).as_bool(); + bool b_signed = st.mul->getParam(ID(B_SIGNED)).as_bool(); + + // Determine DSP type or discard if too narrow / wide + RTLIL::IdString type; + size_t tgt_a_width; + size_t tgt_b_width; + size_t tgt_z_width; + + string cell_base_name = "dsp_t1"; + string cell_size_name = ""; + string cell_cfg_name = ""; + string cell_full_name = ""; + + if (min_width <= 2 && max_width <= 2 && z_width <= 4) { + // Too narrow + return; + } else if (min_width <= 9 && max_width <= 10 && z_width <= 19) { + cell_size_name = "_10x9x32"; + tgt_a_width = 10; + tgt_b_width = 9; + tgt_z_width = 19; + } else if (min_width <= 18 && max_width <= 20 && z_width <= 38) { + cell_size_name = "_20x18x64"; + tgt_a_width = 20; + tgt_b_width = 18; + tgt_z_width = 38; + } else { + // Too wide + return; + } + + if (use_dsp_cfg_params) + cell_cfg_name = "_cfg_params"; + else + cell_cfg_name = "_cfg_ports"; + + cell_full_name = cell_base_name + cell_size_name + cell_cfg_name; + + type = RTLIL::escape_id(cell_full_name); + log("Inferring MACC %zux%zu->%zu as %s from:\n", a_width, b_width, z_width, RTLIL::unescape_id(type).c_str()); + + for (auto cell : {st.mul, st.add, st.mux, st.ff}) { + if (cell != nullptr) { + log(" %s (%s)\n", RTLIL::unescape_id(cell->name).c_str(), RTLIL::unescape_id(cell->type).c_str()); + } + } + + // Build the DSP cell name + std::string name; + name += RTLIL::unescape_id(st.mul->name) + "_"; + name += RTLIL::unescape_id(st.add->name) + "_"; + if (st.mux != nullptr) { + name += RTLIL::unescape_id(st.mux->name) + "_"; + } + name += RTLIL::unescape_id(st.ff->name); + + // Add the DSP cell + RTLIL::Cell *cell = pm.module->addCell(RTLIL::escape_id(name), type); + + // Set attributes + cell->set_bool_attribute(RTLIL::escape_id("is_inferred"), true); + + // Get input/output data signals + RTLIL::SigSpec sig_a; + RTLIL::SigSpec sig_b; + RTLIL::SigSpec sig_z; + + if (a_width >= b_width) { + sig_a = st.mul->getPort(ID(A)); + sig_b = st.mul->getPort(ID(B)); + } else { + sig_a = st.mul->getPort(ID(B)); + sig_b = st.mul->getPort(ID(A)); + } + + sig_z = out_ff ? st.ff->getPort(ID(Q)) : st.ff->getPort(ID(D)); + + // Connect input data ports, sign extend / pad with zeros + sig_a.extend_u0(tgt_a_width, a_signed); + sig_b.extend_u0(tgt_b_width, b_signed); + cell->setPort(RTLIL::escape_id("a_i"), sig_a); + cell->setPort(RTLIL::escape_id("b_i"), sig_b); + + // Connect output data port, pad if needed + if ((size_t)GetSize(sig_z) < tgt_z_width) { + auto *wire = pm.module->addWire(NEW_ID, tgt_z_width - GetSize(sig_z)); + sig_z.append(wire); + } + cell->setPort(RTLIL::escape_id("z_o"), sig_z); + + // Connect clock, reset and enable + cell->setPort(RTLIL::escape_id("clock_i"), st.ff->getPort(ID(CLK))); + + RTLIL::SigSpec rst; + RTLIL::SigSpec ena; + + if (st.ff->hasPort(ID(ARST))) { + if (st.ff->getParam(ID(ARST_POLARITY)).as_int() != 1) { + rst = pm.module->Not(NEW_ID, st.ff->getPort(ID(ARST))); + } else { + rst = st.ff->getPort(ID(ARST)); + } + } else { + rst = RTLIL::SigSpec(RTLIL::S0); + } + + if (st.ff->hasPort(ID(EN))) { + if (st.ff->getParam(ID(EN_POLARITY)).as_int() != 1) { + ena = pm.module->Not(NEW_ID, st.ff->getPort(ID(EN))); + } else { + ena = st.ff->getPort(ID(EN)); + } + } else { + ena = RTLIL::SigSpec(RTLIL::S1); + } + + cell->setPort(RTLIL::escape_id("reset_i"), rst); + cell->setPort(RTLIL::escape_id("load_acc_i"), ena); + + // Insert feedback_i control logic used for clearing / loading the accumulator + if (st.mux != nullptr) { + RTLIL::SigSpec sig_s = st.mux->getPort(ID(S)); + + // Depending on the mux port ordering insert inverter if needed + log_assert(st.mux_ab == ID(A) || st.mux_ab == ID(B)); + if (st.mux_ab == ID(A)) { + sig_s = pm.module->Not(NEW_ID, sig_s); + } + + // Assemble the full control signal for the feedback_i port + RTLIL::SigSpec sig_f; + sig_f.append(sig_s); + sig_f.append(RTLIL::S0); + sig_f.append(RTLIL::S0); + cell->setPort(RTLIL::escape_id("feedback_i"), sig_f); + } + // No acc clear/load + else { + cell->setPort(RTLIL::escape_id("feedback_i"), RTLIL::SigSpec(RTLIL::S0, 3)); + } + + // Connect control ports + cell->setPort(RTLIL::escape_id("unsigned_a_i"), RTLIL::SigSpec(a_signed ? RTLIL::S0 : RTLIL::S1)); + cell->setPort(RTLIL::escape_id("unsigned_b_i"), RTLIL::SigSpec(b_signed ? RTLIL::S0 : RTLIL::S1)); + + // Connect config bits + if (use_dsp_cfg_params) { + cell->setParam(RTLIL::escape_id("SATURATE_ENABLE"), RTLIL::Const(RTLIL::S0)); + cell->setParam(RTLIL::escape_id("SHIFT_RIGHT"), RTLIL::Const(RTLIL::S0, 6)); + cell->setParam(RTLIL::escape_id("ROUND"), RTLIL::Const(RTLIL::S0)); + cell->setParam(RTLIL::escape_id("REGISTER_INPUTS"), RTLIL::Const(RTLIL::S0)); + // 3 - output post acc; 1 - output pre acc + cell->setParam(RTLIL::escape_id("OUTPUT_SELECT"), out_ff ? RTLIL::Const(1, 3) : RTLIL::Const(3, 3)); + } else { + cell->setPort(RTLIL::escape_id("saturate_enable_i"), RTLIL::SigSpec(RTLIL::S0)); + cell->setPort(RTLIL::escape_id("shift_right_i"), RTLIL::SigSpec(RTLIL::S0, 6)); + cell->setPort(RTLIL::escape_id("round_i"), RTLIL::SigSpec(RTLIL::S0)); + cell->setPort(RTLIL::escape_id("register_inputs_i"), RTLIL::SigSpec(RTLIL::S0)); + // 3 - output post acc; 1 - output pre acc + cell->setPort(RTLIL::escape_id("output_select_i"), out_ff ? RTLIL::Const(1, 3) : RTLIL::Const(3, 3)); + } + + bool subtract = (st.add->type == RTLIL::escape_id("$sub")); + cell->setPort(RTLIL::escape_id("subtract_i"), RTLIL::SigSpec(subtract ? RTLIL::S1 : RTLIL::S0)); + + // Mark the cells for removal + pm.autoremove(st.mul); + pm.autoremove(st.add); + if (st.mux != nullptr) { + pm.autoremove(st.mux); + } + pm.autoremove(st.ff); +} + +struct QlDspMacc : public Pass { + + QlDspMacc() : Pass("ql_dsp_macc", "Does something") {} + + void help() override + { + log("\n"); + log(" ql_dsp_macc [options] [selection]\n"); + log("\n"); + log(" -use_dsp_cfg_params\n"); + log(" By default use DSP blocks with configuration bits available at module ports.\n"); + log(" Specifying this forces usage of DSP block with configuration bits available as module parameters\n"); + log("\n"); + } + + void clear_flags() override { use_dsp_cfg_params = false; } + + void execute(std::vector a_Args, RTLIL::Design *a_Design) override + { + log_header(a_Design, "Executing QL_DSP_MACC pass.\n"); + + size_t argidx; + for (argidx = 1; argidx < a_Args.size(); argidx++) { + if (a_Args[argidx] == "-use_dsp_cfg_params") { + use_dsp_cfg_params = true; + continue; + } + + break; + } + extra_args(a_Args, argidx, a_Design); + + for (auto module : a_Design->selected_modules()) { + ql_dsp_macc_pm(module, module->selected_cells()).run_ql_dsp_macc(create_ql_macc_dsp); + } + } + +} QlDspMacc; + +PRIVATE_NAMESPACE_END diff --git a/techlibs/quicklogic/ql_dsp_macc.pmg b/techlibs/quicklogic/ql_dsp_macc.pmg new file mode 100644 index 000000000..4cfd15a24 --- /dev/null +++ b/techlibs/quicklogic/ql_dsp_macc.pmg @@ -0,0 +1,50 @@ +pattern ql_dsp_macc + +state add_ba +state mux_ab + +state mul_nusers +state add_nusers +state mux_nusers +state ff_d_nusers +state ff_q_nusers + +match mul + select mul->type.in($mul) + select nusers(port(mul, \Y)) <= 3 + set mul_nusers nusers(port(mul, \Y)) +endmatch + +match add + select add->type.in($add, $sub) + choice AB {\A, \B} + define BA (AB == \A ? \B : \A) + index port(add, AB) === port(mul, \Y) + select nusers(port(add, \Y)) <= 3 + set add_nusers nusers(port(add, \Y)) + set add_ba BA +endmatch + +match mux + select mux->type.in($mux) + choice AB {\A, \B} + define BA (AB == \A ? \B : \A) + index port(mux, AB) === port(mul, \Y) + index port(mux, BA) === port(add, \Y) + select nusers(port(mux, \Y)) <= 3 + set mux_nusers nusers(port(mux, \Y)) + set mux_ab AB + optional +endmatch + +match ff + select ff->type.in($dff, $adff, $dffe, $adffe) + index port(ff, \D) === (mux == nullptr ? port(add, \Y) : port(mux, \Y)) + index port(ff, \Q) === port(add, add_ba) + set ff_d_nusers nusers(port(ff, \D)) + set ff_q_nusers nusers(port(ff, \Q)) +endmatch + +code + accept; +endcode diff --git a/techlibs/quicklogic/ql_dsp_simd.cc b/techlibs/quicklogic/ql_dsp_simd.cc new file mode 100644 index 000000000..5213aa1c4 --- /dev/null +++ b/techlibs/quicklogic/ql_dsp_simd.cc @@ -0,0 +1,359 @@ +/* + * Copyright 2020-2022 F4PGA Authors + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "kernel/log.h" +#include "kernel/register.h" +#include "kernel/rtlil.h" +#include "kernel/sigtools.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +#define MODE_BITS_BASE_SIZE 80 +#define MODE_BITS_EXTENSION_SIZE 13 + +// ============================================================================ + +struct QlDspSimdPass : public Pass { + + QlDspSimdPass() : Pass("ql_dsp_simd", "Infers QuickLogic k6n10f DSP pairs that can operate in SIMD mode") {} + + void help() override + { + log("\n"); + log(" ql_dsp_simd [selection]\n"); + log("\n"); + log(" This pass identifies k6n10f DSP cells with identical configuration\n"); + log(" and packs pairs of them together into other DSP cells that can\n"); + log(" perform SIMD operation.\n"); + } + + // .......................................... + + /// Describes DSP config unique to a whole DSP cell + struct DspConfig { + + // Port connections + dict connections; + + // Whether DSPs pass configuration bits through ports of parameters + bool use_cfg_params; + + // TODO: Possibly include parameters here. For now we have just + // connections. + + DspConfig() = default; + + DspConfig(const DspConfig &ref) = default; + DspConfig(DspConfig &&ref) = default; + + unsigned int hash() const { return connections.hash(); } + + bool operator==(const DspConfig &ref) const { return connections == ref.connections && use_cfg_params == ref.use_cfg_params; } + }; + + // .......................................... + + // DSP control and config ports to consider and how to map them to ports + // of the target DSP cell + const std::vector> m_DspCfgPorts = {std::make_pair("clock_i", "clk"), + std::make_pair("reset_i", "reset"), + + std::make_pair("feedback_i", "feedback"), + std::make_pair("load_acc_i", "load_acc"), + std::make_pair("unsigned_a_i", "unsigned_a"), + std::make_pair("unsigned_b_i", "unsigned_b"), + + std::make_pair("subtract_i", "subtract")}; + // For QL_DSP2 expand with configuration ports + const std::vector> m_DspCfgPorts_expand = { + std::make_pair("output_select_i", "output_select"), std::make_pair("saturate_enable_i", "saturate_enable"), + std::make_pair("shift_right_i", "shift_right"), std::make_pair("round_i", "round"), std::make_pair("register_inputs_i", "register_inputs")}; + + // For QL_DSP3 use parameters instead + const std::vector m_DspParams2Mode = {"OUTPUT_SELECT", "SATURATE_ENABLE", "SHIFT_RIGHT", "ROUND", "REGISTER_INPUTS"}; + + // DSP data ports and how to map them to ports of the target DSP cell + const std::vector> m_DspDataPorts = { + std::make_pair("a_i", "a"), std::make_pair("b_i", "b"), std::make_pair("acc_fir_i", "acc_fir"), + std::make_pair("z_o", "z"), std::make_pair("dly_b_o", "dly_b"), + }; + + // DSP parameters + const std::vector m_DspParams = {"COEFF_3", "COEFF_2", "COEFF_1", "COEFF_0"}; + + // Source DSP cell type (SISD) + const std::string m_SisdDspType = "dsp_t1_10x9x32"; + // Suffix for DSP cell with configuration parameters + const std::string m_SisdDspType_cfg_params_suffix = "_cfg_params"; + + // Target DSP cell types for the SIMD mode + const std::string m_SimdDspType_cfg_ports = "QL_DSP2"; + const std::string m_SimdDspType_cfg_params = "QL_DSP3"; + + /// Temporary SigBit to SigBit helper map. + SigMap m_SigMap; + + // .......................................... + + void execute(std::vector a_Args, RTLIL::Design *a_Design) override + { + log_header(a_Design, "Executing QL_DSP_SIMD pass.\n"); + + // Parse args + extra_args(a_Args, 1, a_Design); + + // Process modules + for (auto module : a_Design->selected_modules()) { + + // Setup the SigMap + m_SigMap.clear(); + m_SigMap.set(module); + + // Assemble DSP cell groups + dict> groups; + for (auto cell : module->selected_cells()) { + + // Check if this is a DSP cell we are looking for (type starts with m_SisdDspType) + if (strncmp(cell->type.c_str(), RTLIL::escape_id(m_SisdDspType).c_str(), RTLIL::escape_id(m_SisdDspType).size()) != 0) { + continue; + } + + // Skip if it has the (* keep *) attribute set + if (cell->has_keep_attr()) { + continue; + } + + // Add to a group + const auto key = getDspConfig(cell); + groups[key].push_back(cell); + } + + std::vector cellsToRemove; + + // Map cell pairs to the target DSP SIMD cell + for (const auto &it : groups) { + const auto &group = it.second; + const auto &config = it.first; + + bool use_cfg_params = config.use_cfg_params; + // Ensure an even number + size_t count = group.size(); + if (count & 1) + count--; + + // Map SIMD pairs + for (size_t i = 0; i < count; i += 2) { + const RTLIL::Cell *dsp_a = group[i]; + const RTLIL::Cell *dsp_b = group[i + 1]; + + std::string name = stringf("simd%ld", i / 2); + std::string SimdDspType; + + if (use_cfg_params) + SimdDspType = m_SimdDspType_cfg_params; + else + SimdDspType = m_SimdDspType_cfg_ports; + + log(" SIMD: %s (%s) + %s (%s) => %s (%s)\n", RTLIL::unescape_id(dsp_a->name).c_str(), RTLIL::unescape_id(dsp_a->type).c_str(), + RTLIL::unescape_id(dsp_b->name).c_str(), RTLIL::unescape_id(dsp_b->type).c_str(), RTLIL::unescape_id(name).c_str(), + SimdDspType.c_str()); + + // Create the new cell + RTLIL::Cell *simd = module->addCell(RTLIL::escape_id(name), RTLIL::escape_id(SimdDspType)); + + // Check if the target cell is known (important to know + // its port widths) + if (!simd->known()) { + log_error(" The target cell type '%s' is not known!", SimdDspType.c_str()); + } + + std::vector> DspCfgPorts = m_DspCfgPorts; + if (!use_cfg_params) + DspCfgPorts.insert(DspCfgPorts.end(), m_DspCfgPorts_expand.begin(), m_DspCfgPorts_expand.end()); + + // Connect common ports + for (const auto &it : DspCfgPorts) { + auto sport = RTLIL::escape_id(it.first); + auto dport = RTLIL::escape_id(it.second); + + simd->setPort(dport, config.connections.at(sport)); + } + + // Connect data ports + for (const auto &it : m_DspDataPorts) { + auto sport = RTLIL::escape_id(it.first); + auto dport = RTLIL::escape_id(it.second); + + size_t width; + bool isOutput; + + std::tie(width, isOutput) = getPortInfo(simd, dport); + + auto getConnection = [&](const RTLIL::Cell *cell) { + RTLIL::SigSpec sigspec; + if (cell->hasPort(sport)) { + const auto &sig = cell->getPort(sport); + sigspec.append(sig); + } + if (sigspec.bits().size() < width / 2) { + if (isOutput) { + for (size_t i = 0; i < width / 2 - sigspec.bits().size(); ++i) { + sigspec.append(RTLIL::SigSpec()); + } + } else { + sigspec.append(RTLIL::SigSpec(RTLIL::Sx, width / 2 - sigspec.bits().size())); + } + } + return sigspec; + }; + + RTLIL::SigSpec sigspec; + sigspec.append(getConnection(dsp_a)); + sigspec.append(getConnection(dsp_b)); + simd->setPort(dport, sigspec); + } + + // Concatenate FIR coefficient parameters into the single + // MODE_BITS parameter + std::vector mode_bits; + for (const auto &it : m_DspParams) { + auto val_a = dsp_a->getParam(RTLIL::escape_id(it)); + auto val_b = dsp_b->getParam(RTLIL::escape_id(it)); + + mode_bits.insert(mode_bits.end(), val_a.begin(), val_a.end()); + mode_bits.insert(mode_bits.end(), val_b.begin(), val_b.end()); + } + long unsigned int mode_bits_size = MODE_BITS_BASE_SIZE; + if (use_cfg_params) { + // Add additional config parameters if necessary + mode_bits.push_back(RTLIL::S1); // MODE_BITS[80] == F_MODE : Enable fractured mode + for (const auto &it : m_DspParams2Mode) { + log_assert(dsp_a->getParam(RTLIL::escape_id(it)) == dsp_b->getParam(RTLIL::escape_id(it))); + auto param = dsp_a->getParam(RTLIL::escape_id(it)); + if (param.size() > 1) { + mode_bits.insert(mode_bits.end(), param.bits.begin(), param.bits.end()); + } else { + mode_bits.push_back(param.bits[0]); + } + } + mode_bits_size += MODE_BITS_EXTENSION_SIZE; + } else { + // Enable the fractured mode by connecting the control + // port. + simd->setPort(RTLIL::escape_id("f_mode"), RTLIL::S1); + } + simd->setParam(RTLIL::escape_id("MODE_BITS"), RTLIL::Const(mode_bits)); + log_assert(mode_bits.size() == mode_bits_size); + + // Handle the "is_inferred" attribute. If one of the fragments + // is not inferred mark the whole DSP as not inferred + bool is_inferred_a = + dsp_a->has_attribute(RTLIL::escape_id("is_inferred")) ? dsp_a->get_bool_attribute(RTLIL::escape_id("is_inferred")) : false; + bool is_inferred_b = + dsp_b->has_attribute(RTLIL::escape_id("is_inferred")) ? dsp_b->get_bool_attribute(RTLIL::escape_id("is_inferred")) : false; + + simd->set_bool_attribute(RTLIL::escape_id("is_inferred"), is_inferred_a && is_inferred_b); + + // Mark DSP parts for removal + cellsToRemove.push_back(dsp_a); + cellsToRemove.push_back(dsp_b); + } + } + + // Remove old cells + for (const auto &cell : cellsToRemove) { + module->remove(const_cast(cell)); + } + } + + // Clear + m_SigMap.clear(); + } + + // .......................................... + + /// Looks up port width and direction in the cell definition and returns it. + /// Returns (0, false) if it cannot be determined. + std::pair getPortInfo(RTLIL::Cell *a_Cell, RTLIL::IdString a_Port) + { + if (!a_Cell->known()) { + return std::make_pair(0, false); + } + + // Get the module defining the cell (the previous condition ensures + // that the pointers are valid) + RTLIL::Module *mod = a_Cell->module->design->module(a_Cell->type); + if (mod == nullptr) { + return std::make_pair(0, false); + } + + // Get the wire representing the port + RTLIL::Wire *wire = mod->wire(a_Port); + if (wire == nullptr) { + return std::make_pair(0, false); + } + + return std::make_pair(wire->width, wire->port_output); + } + + /// Given a DSP cell populates and returns a DspConfig struct for it. + DspConfig getDspConfig(RTLIL::Cell *a_Cell) + { + DspConfig config; + + string cell_type = a_Cell->type.str(); + string suffix = m_SisdDspType_cfg_params_suffix; + + bool use_cfg_params = cell_type.size() >= suffix.size() && 0 == cell_type.compare(cell_type.size() - suffix.size(), suffix.size(), suffix); + + std::vector> DspCfgPorts = m_DspCfgPorts; + if (!use_cfg_params) + DspCfgPorts.insert(DspCfgPorts.end(), m_DspCfgPorts_expand.begin(), m_DspCfgPorts_expand.end()); + + config.use_cfg_params = use_cfg_params; + + for (const auto &it : DspCfgPorts) { + auto port = RTLIL::escape_id(it.first); + + // Port unconnected + if (!a_Cell->hasPort(port)) { + config.connections[port] = RTLIL::SigSpec(RTLIL::Sx); + continue; + } + + // Get the port connection and map it to unique SigBits + const auto &orgSigSpec = a_Cell->getPort(port); + const auto &orgSigBits = orgSigSpec.bits(); + + RTLIL::SigSpec newSigSpec; + for (size_t i = 0; i < orgSigBits.size(); ++i) { + auto newSigBit = m_SigMap(orgSigBits[i]); + newSigSpec.append(newSigBit); + } + + // Store + config.connections[port] = newSigSpec; + } + + return config; + } + +} QlDspSimdPass; + +PRIVATE_NAMESPACE_END diff --git a/techlibs/quicklogic/qlf_k6n10f/dsp_final_map.v b/techlibs/quicklogic/qlf_k6n10f/dsp_final_map.v new file mode 100644 index 000000000..9eae617b9 --- /dev/null +++ b/techlibs/quicklogic/qlf_k6n10f/dsp_final_map.v @@ -0,0 +1,265 @@ +// Copyright 2020-2022 F4PGA Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 + +module dsp_t1_20x18x64_cfg_ports ( + input [19:0] a_i, + input [17:0] b_i, + input [ 5:0] acc_fir_i, + output [37:0] z_o, + output [17:0] dly_b_o, + + input clock_i, + input reset_i, + + input [2:0] feedback_i, + input load_acc_i, + input unsigned_a_i, + input unsigned_b_i, + + input [2:0] output_select_i, + input saturate_enable_i, + input [5:0] shift_right_i, + input round_i, + input subtract_i, + input register_inputs_i +); + + parameter [19:0] COEFF_0 = 20'd0; + parameter [19:0] COEFF_1 = 20'd0; + parameter [19:0] COEFF_2 = 20'd0; + parameter [19:0] COEFF_3 = 20'd0; + + QL_DSP2 # ( + .MODE_BITS ({COEFF_3, COEFF_2, COEFF_1, COEFF_0}) + ) _TECHMAP_REPLACE_ ( + .a (a_i), + .b (b_i), + .acc_fir (acc_fir_i), + .z (z_o), + .dly_b (dly_b_o), + + .clk (clock_i), + .reset (reset_i), + + .feedback (feedback_i), + .load_acc (load_acc_i), + .unsigned_a (unsigned_a_i), + .unsigned_b (unsigned_b_i), + + .f_mode (1'b0), // No fracturation + .output_select (output_select_i), + .saturate_enable (saturate_enable_i), + .shift_right (shift_right_i), + .round (round_i), + .subtract (subtract_i), + .register_inputs (register_inputs_i) + ); + +endmodule + +module dsp_t1_10x9x32_cfg_ports ( + input [ 9:0] a_i, + input [ 8:0] b_i, + input [ 5:0] acc_fir_i, + output [18:0] z_o, + output [ 8:0] dly_b_o, + + (* clkbuf_sink *) + input clock_i, + input reset_i, + + input [2:0] feedback_i, + input load_acc_i, + input unsigned_a_i, + input unsigned_b_i, + + input [2:0] output_select_i, + input saturate_enable_i, + input [5:0] shift_right_i, + input round_i, + input subtract_i, + input register_inputs_i +); + + parameter [9:0] COEFF_0 = 10'd0; + parameter [9:0] COEFF_1 = 10'd0; + parameter [9:0] COEFF_2 = 10'd0; + parameter [9:0] COEFF_3 = 10'd0; + + wire [37:0] z; + wire [17:0] dly_b; + + QL_DSP2 # ( + .MODE_BITS ({10'd0, COEFF_3, + 10'd0, COEFF_2, + 10'd0, COEFF_1, + 10'd0, COEFF_0}) + ) _TECHMAP_REPLACE_ ( + .a ({10'd0, a_i}), + .b ({ 9'd0, b_i}), + .acc_fir (acc_fir_i), + .z (z), + .dly_b (dly_b), + + .clk (clock_i), + .reset (reset_i), + + .feedback (feedback_i), + .load_acc (load_acc_i), + .unsigned_a (unsigned_a_i), + .unsigned_b (unsigned_b_i), + + .f_mode (1'b1), // Enable fractuation, Use the lower half + .output_select (output_select_i), + .saturate_enable (saturate_enable_i), + .shift_right (shift_right_i), + .round (round_i), + .subtract (subtract_i), + .register_inputs (register_inputs_i) + ); + + assign z_o = z[18:0]; + assign dly_b_o = dly_b_o[8:0]; + +endmodule + +module dsp_t1_20x18x64_cfg_params ( + input [19:0] a_i, + input [17:0] b_i, + input [ 5:0] acc_fir_i, + output [37:0] z_o, + output [17:0] dly_b_o, + + input clock_i, + input reset_i, + + input [2:0] feedback_i, + input load_acc_i, + input unsigned_a_i, + input unsigned_b_i, + input subtract_i +); + + parameter [19:0] COEFF_0 = 20'd0; + parameter [19:0] COEFF_1 = 20'd0; + parameter [19:0] COEFF_2 = 20'd0; + parameter [19:0] COEFF_3 = 20'd0; + + parameter [2:0] OUTPUT_SELECT = 3'd0; + parameter [0:0] SATURATE_ENABLE = 1'd0; + parameter [5:0] SHIFT_RIGHT = 6'd0; + parameter [0:0] ROUND = 1'd0; + parameter [0:0] REGISTER_INPUTS = 1'd0; + + QL_DSP3 # ( + .MODE_BITS ({ + REGISTER_INPUTS, + ROUND, + SHIFT_RIGHT, + SATURATE_ENABLE, + OUTPUT_SELECT, + 1'b0, // Not fractured + COEFF_3, + COEFF_2, + COEFF_1, + COEFF_0 + }) + ) _TECHMAP_REPLACE_ ( + .a (a_i), + .b (b_i), + .acc_fir (acc_fir_i), + .z (z_o), + .dly_b (dly_b_o), + + .clk (clock_i), + .reset (reset_i), + + .feedback (feedback_i), + .load_acc (load_acc_i), + .unsigned_a (unsigned_a_i), + .unsigned_b (unsigned_b_i), + .subtract (subtract_i) + ); + +endmodule + +module dsp_t1_10x9x32_cfg_params ( + input [ 9:0] a_i, + input [ 8:0] b_i, + input [ 5:0] acc_fir_i, + output [18:0] z_o, + output [ 8:0] dly_b_o, + + (* clkbuf_sink *) + input clock_i, + input reset_i, + + input [2:0] feedback_i, + input load_acc_i, + input unsigned_a_i, + input unsigned_b_i, + input subtract_i +); + + parameter [9:0] COEFF_0 = 10'd0; + parameter [9:0] COEFF_1 = 10'd0; + parameter [9:0] COEFF_2 = 10'd0; + parameter [9:0] COEFF_3 = 10'd0; + + parameter [2:0] OUTPUT_SELECT = 3'd0; + parameter [0:0] SATURATE_ENABLE = 1'd0; + parameter [5:0] SHIFT_RIGHT = 6'd0; + parameter [0:0] ROUND = 1'd0; + parameter [0:0] REGISTER_INPUTS = 1'd0; + + wire [37:0] z; + wire [17:0] dly_b; + + QL_DSP3 # ( + .MODE_BITS ({ + REGISTER_INPUTS, + ROUND, + SHIFT_RIGHT, + SATURATE_ENABLE, + OUTPUT_SELECT, + 1'b1, // Fractured + 10'd0, COEFF_3, + 10'd0, COEFF_2, + 10'd0, COEFF_1, + 10'd0, COEFF_0 + }) + ) _TECHMAP_REPLACE_ ( + .a ({10'd0, a_i}), + .b ({ 9'd0, b_i}), + .acc_fir (acc_fir_i), + .z (z), + .dly_b (dly_b), + + .clk (clock_i), + .reset (reset_i), + + .feedback (feedback_i), + .load_acc (load_acc_i), + .unsigned_a (unsigned_a_i), + .unsigned_b (unsigned_b_i), + .subtract (subtract_i) + ); + + assign z_o = z[18:0]; + assign dly_b_o = dly_b_o[8:0]; + +endmodule + diff --git a/techlibs/quicklogic/qlf_k6n10f/dsp_map.v b/techlibs/quicklogic/qlf_k6n10f/dsp_map.v new file mode 100644 index 000000000..bb9f05283 --- /dev/null +++ b/techlibs/quicklogic/qlf_k6n10f/dsp_map.v @@ -0,0 +1,147 @@ +// Copyright 2020-2022 F4PGA Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 + +module \$__QL_MUL20X18 (input [19:0] A, input [17:0] B, output [37:0] Y); + parameter A_SIGNED = 0; + parameter B_SIGNED = 0; + parameter A_WIDTH = 0; + parameter B_WIDTH = 0; + parameter Y_WIDTH = 0; + + wire [19:0] a; + wire [17:0] b; + wire [37:0] z; + + assign a = (A_WIDTH == 20) ? A : + (A_SIGNED) ? {{(20 - A_WIDTH){A[A_WIDTH-1]}}, A} : + {{(20 - A_WIDTH){1'b0}}, A}; + + assign b = (B_WIDTH == 18) ? B : + (B_SIGNED) ? {{(18 - B_WIDTH){B[B_WIDTH-1]}}, B} : + {{(18 - B_WIDTH){1'b0}}, B}; + + generate if (`USE_DSP_CFG_PARAMS == 0) begin + (* is_inferred=1 *) + dsp_t1_20x18x64_cfg_ports _TECHMAP_REPLACE_ ( + .a_i (a), + .b_i (b), + .acc_fir_i (6'd0), + .z_o (z), + + .feedback_i (3'd0), + .load_acc_i (1'b0), + .unsigned_a_i (!A_SIGNED), + .unsigned_b_i (!B_SIGNED), + + .output_select_i (3'd0), + .saturate_enable_i (1'b0), + .shift_right_i (6'd0), + .round_i (1'b0), + .subtract_i (1'b0), + .register_inputs_i (1'b0) + ); + end else begin + (* is_inferred=1 *) + dsp_t1_20x18x64_cfg_params #( + .OUTPUT_SELECT (3'd0), + .SATURATE_ENABLE (1'b0), + .SHIFT_RIGHT (6'd0), + .ROUND (1'b0), + .REGISTER_INPUTS (1'b0) + ) TECHMAP_REPLACE_ ( + .a_i (a), + .b_i (b), + .acc_fir_i (6'd0), + .z_o (z), + + .feedback_i (3'd0), + .load_acc_i (1'b0), + .unsigned_a_i (!A_SIGNED), + .unsigned_b_i (!B_SIGNED), + + .subtract_i (1'b0) + ); + end endgenerate + + assign Y = z; + +endmodule + +module \$__QL_MUL10X9 (input [9:0] A, input [8:0] B, output [18:0] Y); + parameter A_SIGNED = 0; + parameter B_SIGNED = 0; + parameter A_WIDTH = 0; + parameter B_WIDTH = 0; + parameter Y_WIDTH = 0; + + wire [ 9:0] a; + wire [ 8:0] b; + wire [18:0] z; + + assign a = (A_WIDTH == 10) ? A : + (A_SIGNED) ? {{(10 - A_WIDTH){A[A_WIDTH-1]}}, A} : + {{(10 - A_WIDTH){1'b0}}, A}; + + assign b = (B_WIDTH == 9) ? B : + (B_SIGNED) ? {{( 9 - B_WIDTH){B[B_WIDTH-1]}}, B} : + {{( 9 - B_WIDTH){1'b0}}, B}; + + generate if (`USE_DSP_CFG_PARAMS == 0) begin + (* is_inferred=1 *) + dsp_t1_10x9x32_cfg_ports _TECHMAP_REPLACE_ ( + .a_i (a), + .b_i (b), + .acc_fir_i (6'd0), + .z_o (z), + + .feedback_i (3'd0), + .load_acc_i (1'b0), + .unsigned_a_i (!A_SIGNED), + .unsigned_b_i (!B_SIGNED), + + .output_select_i (3'd0), + .saturate_enable_i (1'b0), + .shift_right_i (6'd0), + .round_i (1'b0), + .subtract_i (1'b0), + .register_inputs_i (1'b0) + ); + end else begin + (* is_inferred=1 *) + dsp_t1_10x9x32_cfg_params #( + .OUTPUT_SELECT (3'd0), + .SATURATE_ENABLE (1'b0), + .SHIFT_RIGHT (6'd0), + .ROUND (1'b0), + .REGISTER_INPUTS (1'b0) + ) TECHMAP_REPLACE_ ( + .a_i (a), + .b_i (b), + .acc_fir_i (6'd0), + .z_o (z), + + .feedback_i (3'd0), + .load_acc_i (1'b0), + .unsigned_a_i (!A_SIGNED), + .unsigned_b_i (!B_SIGNED), + + .subtract_i (1'b0) + ); + end endgenerate + + assign Y = z; + +endmodule diff --git a/techlibs/quicklogic/qlf_k6n10f/dsp_sim.v b/techlibs/quicklogic/qlf_k6n10f/dsp_sim.v new file mode 100644 index 000000000..05a4835e8 --- /dev/null +++ b/techlibs/quicklogic/qlf_k6n10f/dsp_sim.v @@ -0,0 +1,5753 @@ +// Copyright 2020-2022 F4PGA Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 + +`timescale 1ps/1ps + +`default_nettype none + +(* blackbox *) +module QL_DSP1 ( + input wire [19:0] a, + input wire [17:0] b, + (* clkbuf_sink *) + input wire clk0, + (* clkbuf_sink *) + input wire clk1, + input wire [ 1:0] feedback0, + input wire [ 1:0] feedback1, + input wire load_acc0, + input wire load_acc1, + input wire reset0, + input wire reset1, + output reg [37:0] z +); + parameter MODE_BITS = 27'b00000000000000000000000000; +endmodule /* QL_DSP1 */ + + + +// ---------------------------------------- // +// ----- DSP cells simulation modules ----- // +// --------- Control bits in ports -------- // +// ---------------------------------------- // + +module QL_DSP2 ( // TODO: Name subject to change + input wire [19:0] a, + input wire [17:0] b, + input wire [ 5:0] acc_fir, + output wire [37:0] z, + output wire [17:0] dly_b, + + (* clkbuf_sink *) + input wire clk, + input wire reset, + + input wire [2:0] feedback, + input wire load_acc, + input wire unsigned_a, + input wire unsigned_b, + + input wire f_mode, + input wire [2:0] output_select, + input wire saturate_enable, + input wire [5:0] shift_right, + input wire round, + input wire subtract, + input wire register_inputs +); + + parameter [79:0] MODE_BITS = 80'd0; + + localparam [19:0] COEFF_0 = MODE_BITS[19:0]; + localparam [19:0] COEFF_1 = MODE_BITS[39:20]; + localparam [19:0] COEFF_2 = MODE_BITS[59:40]; + localparam [19:0] COEFF_3 = MODE_BITS[79:60]; + + localparam NBITS_ACC = 64; + localparam NBITS_A = 20; + localparam NBITS_B = 18; + localparam NBITS_Z = 38; + + wire [NBITS_Z-1:0] dsp_full_z; + wire [(NBITS_Z/2)-1:0] dsp_frac0_z; + wire [(NBITS_Z/2)-1:0] dsp_frac1_z; + + wire [NBITS_B-1:0] dsp_full_dly_b; + wire [(NBITS_B/2)-1:0] dsp_frac0_dly_b; + wire [(NBITS_B/2)-1:0] dsp_frac1_dly_b; + + assign z = f_mode ? {dsp_frac1_z, dsp_frac0_z} : dsp_full_z; + assign dly_b = f_mode ? {dsp_frac1_dly_b, dsp_frac0_dly_b} : dsp_full_dly_b; + + // Output used when fmode == 1 + dsp_t1_sim_cfg_ports #( + .NBITS_A(NBITS_A/2), + .NBITS_B(NBITS_B/2), + .NBITS_ACC(NBITS_ACC/2), + .NBITS_Z(NBITS_Z/2) + ) dsp_frac0 ( + .a_i(a[(NBITS_A/2)-1:0]), + .b_i(b[(NBITS_B/2)-1:0]), + .z_o(dsp_frac0_z), + .dly_b_o(dsp_frac0_dly_b), + + .acc_fir_i(acc_fir), + .feedback_i(feedback), + .load_acc_i(load_acc), + + .unsigned_a_i(unsigned_a), + .unsigned_b_i(unsigned_b), + + .clock_i(clk), + .s_reset(reset), + + .saturate_enable_i(saturate_enable), + .output_select_i(output_select), + .round_i(round), + .shift_right_i(shift_right), + .subtract_i(subtract), + .register_inputs_i(register_inputs), + .coef_0_i(COEFF_0[(NBITS_A/2)-1:0]), + .coef_1_i(COEFF_1[(NBITS_A/2)-1:0]), + .coef_2_i(COEFF_2[(NBITS_A/2)-1:0]), + .coef_3_i(COEFF_3[(NBITS_A/2)-1:0]) + ); + + // Output used when fmode == 1 + dsp_t1_sim_cfg_ports #( + .NBITS_A(NBITS_A/2), + .NBITS_B(NBITS_B/2), + .NBITS_ACC(NBITS_ACC/2), + .NBITS_Z(NBITS_Z/2) + ) dsp_frac1 ( + .a_i(a[NBITS_A-1:NBITS_A/2]), + .b_i(b[NBITS_B-1:NBITS_B/2]), + .z_o(dsp_frac1_z), + .dly_b_o(dsp_frac1_dly_b), + + .acc_fir_i(acc_fir), + .feedback_i(feedback), + .load_acc_i(load_acc), + + .unsigned_a_i(unsigned_a), + .unsigned_b_i(unsigned_b), + + .clock_i(clk), + .s_reset(reset), + + .saturate_enable_i(saturate_enable), + .output_select_i(output_select), + .round_i(round), + .shift_right_i(shift_right), + .subtract_i(subtract), + .register_inputs_i(register_inputs), + .coef_0_i(COEFF_0[NBITS_A-1:NBITS_A/2]), + .coef_1_i(COEFF_1[NBITS_A-1:NBITS_A/2]), + .coef_2_i(COEFF_2[NBITS_A-1:NBITS_A/2]), + .coef_3_i(COEFF_3[NBITS_A-1:NBITS_A/2]) + ); + + // Output used when fmode == 0 + dsp_t1_sim_cfg_ports #( + .NBITS_A(NBITS_A), + .NBITS_B(NBITS_B), + .NBITS_ACC(NBITS_ACC), + .NBITS_Z(NBITS_Z) + ) dsp_full ( + .a_i(a), + .b_i(b), + .z_o(dsp_full_z), + .dly_b_o(dsp_full_dly_b), + + .acc_fir_i(acc_fir), + .feedback_i(feedback), + .load_acc_i(load_acc), + + .unsigned_a_i(unsigned_a), + .unsigned_b_i(unsigned_b), + + .clock_i(clk), + .s_reset(reset), + + .saturate_enable_i(saturate_enable), + .output_select_i(output_select), + .round_i(round), + .shift_right_i(shift_right), + .subtract_i(subtract), + .register_inputs_i(register_inputs), + .coef_0_i(COEFF_0), + .coef_1_i(COEFF_1), + .coef_2_i(COEFF_2), + .coef_3_i(COEFF_3) + ); +endmodule + +module QL_DSP2_MULT ( // TODO: Name subject to change + input wire [19:0] a, + input wire [17:0] b, + output wire [37:0] z, + + input wire reset, + + input wire [2:0] feedback, + input wire unsigned_a, + input wire unsigned_b, + + input wire f_mode, + input wire [2:0] output_select, + input wire register_inputs +); + + parameter [79:0] MODE_BITS = 80'd0; + + localparam [19:0] COEFF_0 = MODE_BITS[19:0]; + localparam [19:0] COEFF_1 = MODE_BITS[39:20]; + localparam [19:0] COEFF_2 = MODE_BITS[59:40]; + localparam [19:0] COEFF_3 = MODE_BITS[79:60]; + + QL_DSP2 #( + .MODE_BITS({COEFF_3, COEFF_2, COEFF_1, COEFF_0}) + ) dsp ( + .a(a), + .b(b), + .acc_fir(6'b0), + .z(z), + .dly_b(), + + .clk(1'b0), + .reset(reset), + + .f_mode(f_mode), + + .feedback(feedback), + .load_acc(1'b0), + + .unsigned_a(unsigned_a), + .unsigned_b(unsigned_b), + + .output_select(output_select), // unregistered output: a * b (0) + .saturate_enable(1'b0), + .shift_right(6'b0), + .round(1'b0), + .subtract(1'b0), + .register_inputs(register_inputs) // unregistered inputs + ); + +`ifdef SDF_SIM + specify + (a[0] => z[0]) = 0; + (a[1] => z[0]) = 0; + (a[2] => z[0]) = 0; + (a[3] => z[0]) = 0; + (a[4] => z[0]) = 0; + (a[5] => z[0]) = 0; + (a[6] => z[0]) = 0; + (a[7] => z[0]) = 0; + (a[8] => z[0]) = 0; + (a[9] => z[0]) = 0; + (a[10] => z[0]) = 0; + (a[11] => z[0]) = 0; + (a[12] => z[0]) = 0; + (a[13] => z[0]) = 0; + (a[14] => z[0]) = 0; + (a[15] => z[0]) = 0; + (a[16] => z[0]) = 0; + (a[17] => z[0]) = 0; + (a[18] => z[0]) = 0; + (a[19] => z[0]) = 0; + (b[0] => z[0]) = 0; + (b[1] => z[0]) = 0; + (b[2] => z[0]) = 0; + (b[3] => z[0]) = 0; + (b[4] => z[0]) = 0; + (b[5] => z[0]) = 0; + (b[6] => z[0]) = 0; + (b[7] => z[0]) = 0; + (b[8] => z[0]) = 0; + (b[9] => z[0]) = 0; + (b[10] => z[0]) = 0; + (b[11] => z[0]) = 0; + (b[12] => z[0]) = 0; + (b[13] => z[0]) = 0; + (b[14] => z[0]) = 0; + (b[15] => z[0]) = 0; + (b[16] => z[0]) = 0; + (b[17] => z[0]) = 0; + (a[0] => z[1]) = 0; + (a[1] => z[1]) = 0; + (a[2] => z[1]) = 0; + (a[3] => z[1]) = 0; + (a[4] => z[1]) = 0; + (a[5] => z[1]) = 0; + (a[6] => z[1]) = 0; + (a[7] => z[1]) = 0; + (a[8] => z[1]) = 0; + (a[9] => z[1]) = 0; + (a[10] => z[1]) = 0; + (a[11] => z[1]) = 0; + (a[12] => z[1]) = 0; + (a[13] => z[1]) = 0; + (a[14] => z[1]) = 0; + (a[15] => z[1]) = 0; + (a[16] => z[1]) = 0; + (a[17] => z[1]) = 0; + (a[18] => z[1]) = 0; + (a[19] => z[1]) = 0; + (b[0] => z[1]) = 0; + (b[1] => z[1]) = 0; + (b[2] => z[1]) = 0; + (b[3] => z[1]) = 0; + (b[4] => z[1]) = 0; + (b[5] => z[1]) = 0; + (b[6] => z[1]) = 0; + (b[7] => z[1]) = 0; + (b[8] => z[1]) = 0; + (b[9] => z[1]) = 0; + (b[10] => z[1]) = 0; + (b[11] => z[1]) = 0; + (b[12] => z[1]) = 0; + (b[13] => z[1]) = 0; + (b[14] => z[1]) = 0; + (b[15] => z[1]) = 0; + (b[16] => z[1]) = 0; + (b[17] => z[1]) = 0; + (a[0] => z[2]) = 0; + (a[1] => z[2]) = 0; + (a[2] => z[2]) = 0; + (a[3] => z[2]) = 0; + (a[4] => z[2]) = 0; + (a[5] => z[2]) = 0; + (a[6] => z[2]) = 0; + (a[7] => z[2]) = 0; + (a[8] => z[2]) = 0; + (a[9] => z[2]) = 0; + (a[10] => z[2]) = 0; + (a[11] => z[2]) = 0; + (a[12] => z[2]) = 0; + (a[13] => z[2]) = 0; + (a[14] => z[2]) = 0; + (a[15] => z[2]) = 0; + (a[16] => z[2]) = 0; + (a[17] => z[2]) = 0; + (a[18] => z[2]) = 0; + (a[19] => z[2]) = 0; + (b[0] => z[2]) = 0; + (b[1] => z[2]) = 0; + (b[2] => z[2]) = 0; + (b[3] => z[2]) = 0; + (b[4] => z[2]) = 0; + (b[5] => z[2]) = 0; + (b[6] => z[2]) = 0; + (b[7] => z[2]) = 0; + (b[8] => z[2]) = 0; + (b[9] => z[2]) = 0; + (b[10] => z[2]) = 0; + (b[11] => z[2]) = 0; + (b[12] => z[2]) = 0; + (b[13] => z[2]) = 0; + (b[14] => z[2]) = 0; + (b[15] => z[2]) = 0; + (b[16] => z[2]) = 0; + (b[17] => z[2]) = 0; + (a[0] => z[3]) = 0; + (a[1] => z[3]) = 0; + (a[2] => z[3]) = 0; + (a[3] => z[3]) = 0; + (a[4] => z[3]) = 0; + (a[5] => z[3]) = 0; + (a[6] => z[3]) = 0; + (a[7] => z[3]) = 0; + (a[8] => z[3]) = 0; + (a[9] => z[3]) = 0; + (a[10] => z[3]) = 0; + (a[11] => z[3]) = 0; + (a[12] => z[3]) = 0; + (a[13] => z[3]) = 0; + (a[14] => z[3]) = 0; + (a[15] => z[3]) = 0; + (a[16] => z[3]) = 0; + (a[17] => z[3]) = 0; + (a[18] => z[3]) = 0; + (a[19] => z[3]) = 0; + (b[0] => z[3]) = 0; + (b[1] => z[3]) = 0; + (b[2] => z[3]) = 0; + (b[3] => z[3]) = 0; + (b[4] => z[3]) = 0; + (b[5] => z[3]) = 0; + (b[6] => z[3]) = 0; + (b[7] => z[3]) = 0; + (b[8] => z[3]) = 0; + (b[9] => z[3]) = 0; + (b[10] => z[3]) = 0; + (b[11] => z[3]) = 0; + (b[12] => z[3]) = 0; + (b[13] => z[3]) = 0; + (b[14] => z[3]) = 0; + (b[15] => z[3]) = 0; + (b[16] => z[3]) = 0; + (b[17] => z[3]) = 0; + (a[0] => z[4]) = 0; + (a[1] => z[4]) = 0; + (a[2] => z[4]) = 0; + (a[3] => z[4]) = 0; + (a[4] => z[4]) = 0; + (a[5] => z[4]) = 0; + (a[6] => z[4]) = 0; + (a[7] => z[4]) = 0; + (a[8] => z[4]) = 0; + (a[9] => z[4]) = 0; + (a[10] => z[4]) = 0; + (a[11] => z[4]) = 0; + (a[12] => z[4]) = 0; + (a[13] => z[4]) = 0; + (a[14] => z[4]) = 0; + (a[15] => z[4]) = 0; + (a[16] => z[4]) = 0; + (a[17] => z[4]) = 0; + (a[18] => z[4]) = 0; + (a[19] => z[4]) = 0; + (b[0] => z[4]) = 0; + (b[1] => z[4]) = 0; + (b[2] => z[4]) = 0; + (b[3] => z[4]) = 0; + (b[4] => z[4]) = 0; + (b[5] => z[4]) = 0; + (b[6] => z[4]) = 0; + (b[7] => z[4]) = 0; + (b[8] => z[4]) = 0; + (b[9] => z[4]) = 0; + (b[10] => z[4]) = 0; + (b[11] => z[4]) = 0; + (b[12] => z[4]) = 0; + (b[13] => z[4]) = 0; + (b[14] => z[4]) = 0; + (b[15] => z[4]) = 0; + (b[16] => z[4]) = 0; + (b[17] => z[4]) = 0; + (a[0] => z[5]) = 0; + (a[1] => z[5]) = 0; + (a[2] => z[5]) = 0; + (a[3] => z[5]) = 0; + (a[4] => z[5]) = 0; + (a[5] => z[5]) = 0; + (a[6] => z[5]) = 0; + (a[7] => z[5]) = 0; + (a[8] => z[5]) = 0; + (a[9] => z[5]) = 0; + (a[10] => z[5]) = 0; + (a[11] => z[5]) = 0; + (a[12] => z[5]) = 0; + (a[13] => z[5]) = 0; + (a[14] => z[5]) = 0; + (a[15] => z[5]) = 0; + (a[16] => z[5]) = 0; + (a[17] => z[5]) = 0; + (a[18] => z[5]) = 0; + (a[19] => z[5]) = 0; + (b[0] => z[5]) = 0; + (b[1] => z[5]) = 0; + (b[2] => z[5]) = 0; + (b[3] => z[5]) = 0; + (b[4] => z[5]) = 0; + (b[5] => z[5]) = 0; + (b[6] => z[5]) = 0; + (b[7] => z[5]) = 0; + (b[8] => z[5]) = 0; + (b[9] => z[5]) = 0; + (b[10] => z[5]) = 0; + (b[11] => z[5]) = 0; + (b[12] => z[5]) = 0; + (b[13] => z[5]) = 0; + (b[14] => z[5]) = 0; + (b[15] => z[5]) = 0; + (b[16] => z[5]) = 0; + (b[17] => z[5]) = 0; + (a[0] => z[6]) = 0; + (a[1] => z[6]) = 0; + (a[2] => z[6]) = 0; + (a[3] => z[6]) = 0; + (a[4] => z[6]) = 0; + (a[5] => z[6]) = 0; + (a[6] => z[6]) = 0; + (a[7] => z[6]) = 0; + (a[8] => z[6]) = 0; + (a[9] => z[6]) = 0; + (a[10] => z[6]) = 0; + (a[11] => z[6]) = 0; + (a[12] => z[6]) = 0; + (a[13] => z[6]) = 0; + (a[14] => z[6]) = 0; + (a[15] => z[6]) = 0; + (a[16] => z[6]) = 0; + (a[17] => z[6]) = 0; + (a[18] => z[6]) = 0; + (a[19] => z[6]) = 0; + (b[0] => z[6]) = 0; + (b[1] => z[6]) = 0; + (b[2] => z[6]) = 0; + (b[3] => z[6]) = 0; + (b[4] => z[6]) = 0; + (b[5] => z[6]) = 0; + (b[6] => z[6]) = 0; + (b[7] => z[6]) = 0; + (b[8] => z[6]) = 0; + (b[9] => z[6]) = 0; + (b[10] => z[6]) = 0; + (b[11] => z[6]) = 0; + (b[12] => z[6]) = 0; + (b[13] => z[6]) = 0; + (b[14] => z[6]) = 0; + (b[15] => z[6]) = 0; + (b[16] => z[6]) = 0; + (b[17] => z[6]) = 0; + (a[0] => z[7]) = 0; + (a[1] => z[7]) = 0; + (a[2] => z[7]) = 0; + (a[3] => z[7]) = 0; + (a[4] => z[7]) = 0; + (a[5] => z[7]) = 0; + (a[6] => z[7]) = 0; + (a[7] => z[7]) = 0; + (a[8] => z[7]) = 0; + (a[9] => z[7]) = 0; + (a[10] => z[7]) = 0; + (a[11] => z[7]) = 0; + (a[12] => z[7]) = 0; + (a[13] => z[7]) = 0; + (a[14] => z[7]) = 0; + (a[15] => z[7]) = 0; + (a[16] => z[7]) = 0; + (a[17] => z[7]) = 0; + (a[18] => z[7]) = 0; + (a[19] => z[7]) = 0; + (b[0] => z[7]) = 0; + (b[1] => z[7]) = 0; + (b[2] => z[7]) = 0; + (b[3] => z[7]) = 0; + (b[4] => z[7]) = 0; + (b[5] => z[7]) = 0; + (b[6] => z[7]) = 0; + (b[7] => z[7]) = 0; + (b[8] => z[7]) = 0; + (b[9] => z[7]) = 0; + (b[10] => z[7]) = 0; + (b[11] => z[7]) = 0; + (b[12] => z[7]) = 0; + (b[13] => z[7]) = 0; + (b[14] => z[7]) = 0; + (b[15] => z[7]) = 0; + (b[16] => z[7]) = 0; + (b[17] => z[7]) = 0; + (a[0] => z[8]) = 0; + (a[1] => z[8]) = 0; + (a[2] => z[8]) = 0; + (a[3] => z[8]) = 0; + (a[4] => z[8]) = 0; + (a[5] => z[8]) = 0; + (a[6] => z[8]) = 0; + (a[7] => z[8]) = 0; + (a[8] => z[8]) = 0; + (a[9] => z[8]) = 0; + (a[10] => z[8]) = 0; + (a[11] => z[8]) = 0; + (a[12] => z[8]) = 0; + (a[13] => z[8]) = 0; + (a[14] => z[8]) = 0; + (a[15] => z[8]) = 0; + (a[16] => z[8]) = 0; + (a[17] => z[8]) = 0; + (a[18] => z[8]) = 0; + (a[19] => z[8]) = 0; + (b[0] => z[8]) = 0; + (b[1] => z[8]) = 0; + (b[2] => z[8]) = 0; + (b[3] => z[8]) = 0; + (b[4] => z[8]) = 0; + (b[5] => z[8]) = 0; + (b[6] => z[8]) = 0; + (b[7] => z[8]) = 0; + (b[8] => z[8]) = 0; + (b[9] => z[8]) = 0; + (b[10] => z[8]) = 0; + (b[11] => z[8]) = 0; + (b[12] => z[8]) = 0; + (b[13] => z[8]) = 0; + (b[14] => z[8]) = 0; + (b[15] => z[8]) = 0; + (b[16] => z[8]) = 0; + (b[17] => z[8]) = 0; + (a[0] => z[9]) = 0; + (a[1] => z[9]) = 0; + (a[2] => z[9]) = 0; + (a[3] => z[9]) = 0; + (a[4] => z[9]) = 0; + (a[5] => z[9]) = 0; + (a[6] => z[9]) = 0; + (a[7] => z[9]) = 0; + (a[8] => z[9]) = 0; + (a[9] => z[9]) = 0; + (a[10] => z[9]) = 0; + (a[11] => z[9]) = 0; + (a[12] => z[9]) = 0; + (a[13] => z[9]) = 0; + (a[14] => z[9]) = 0; + (a[15] => z[9]) = 0; + (a[16] => z[9]) = 0; + (a[17] => z[9]) = 0; + (a[18] => z[9]) = 0; + (a[19] => z[9]) = 0; + (b[0] => z[9]) = 0; + (b[1] => z[9]) = 0; + (b[2] => z[9]) = 0; + (b[3] => z[9]) = 0; + (b[4] => z[9]) = 0; + (b[5] => z[9]) = 0; + (b[6] => z[9]) = 0; + (b[7] => z[9]) = 0; + (b[8] => z[9]) = 0; + (b[9] => z[9]) = 0; + (b[10] => z[9]) = 0; + (b[11] => z[9]) = 0; + (b[12] => z[9]) = 0; + (b[13] => z[9]) = 0; + (b[14] => z[9]) = 0; + (b[15] => z[9]) = 0; + (b[16] => z[9]) = 0; + (b[17] => z[9]) = 0; + (a[0] => z[10]) = 0; + (a[1] => z[10]) = 0; + (a[2] => z[10]) = 0; + (a[3] => z[10]) = 0; + (a[4] => z[10]) = 0; + (a[5] => z[10]) = 0; + (a[6] => z[10]) = 0; + (a[7] => z[10]) = 0; + (a[8] => z[10]) = 0; + (a[9] => z[10]) = 0; + (a[10] => z[10]) = 0; + (a[11] => z[10]) = 0; + (a[12] => z[10]) = 0; + (a[13] => z[10]) = 0; + (a[14] => z[10]) = 0; + (a[15] => z[10]) = 0; + (a[16] => z[10]) = 0; + (a[17] => z[10]) = 0; + (a[18] => z[10]) = 0; + (a[19] => z[10]) = 0; + (b[0] => z[10]) = 0; + (b[1] => z[10]) = 0; + (b[2] => z[10]) = 0; + (b[3] => z[10]) = 0; + (b[4] => z[10]) = 0; + (b[5] => z[10]) = 0; + (b[6] => z[10]) = 0; + (b[7] => z[10]) = 0; + (b[8] => z[10]) = 0; + (b[9] => z[10]) = 0; + (b[10] => z[10]) = 0; + (b[11] => z[10]) = 0; + (b[12] => z[10]) = 0; + (b[13] => z[10]) = 0; + (b[14] => z[10]) = 0; + (b[15] => z[10]) = 0; + (b[16] => z[10]) = 0; + (b[17] => z[10]) = 0; + (a[0] => z[11]) = 0; + (a[1] => z[11]) = 0; + (a[2] => z[11]) = 0; + (a[3] => z[11]) = 0; + (a[4] => z[11]) = 0; + (a[5] => z[11]) = 0; + (a[6] => z[11]) = 0; + (a[7] => z[11]) = 0; + (a[8] => z[11]) = 0; + (a[9] => z[11]) = 0; + (a[10] => z[11]) = 0; + (a[11] => z[11]) = 0; + (a[12] => z[11]) = 0; + (a[13] => z[11]) = 0; + (a[14] => z[11]) = 0; + (a[15] => z[11]) = 0; + (a[16] => z[11]) = 0; + (a[17] => z[11]) = 0; + (a[18] => z[11]) = 0; + (a[19] => z[11]) = 0; + (b[0] => z[11]) = 0; + (b[1] => z[11]) = 0; + (b[2] => z[11]) = 0; + (b[3] => z[11]) = 0; + (b[4] => z[11]) = 0; + (b[5] => z[11]) = 0; + (b[6] => z[11]) = 0; + (b[7] => z[11]) = 0; + (b[8] => z[11]) = 0; + (b[9] => z[11]) = 0; + (b[10] => z[11]) = 0; + (b[11] => z[11]) = 0; + (b[12] => z[11]) = 0; + (b[13] => z[11]) = 0; + (b[14] => z[11]) = 0; + (b[15] => z[11]) = 0; + (b[16] => z[11]) = 0; + (b[17] => z[11]) = 0; + (a[0] => z[12]) = 0; + (a[1] => z[12]) = 0; + (a[2] => z[12]) = 0; + (a[3] => z[12]) = 0; + (a[4] => z[12]) = 0; + (a[5] => z[12]) = 0; + (a[6] => z[12]) = 0; + (a[7] => z[12]) = 0; + (a[8] => z[12]) = 0; + (a[9] => z[12]) = 0; + (a[10] => z[12]) = 0; + (a[11] => z[12]) = 0; + (a[12] => z[12]) = 0; + (a[13] => z[12]) = 0; + (a[14] => z[12]) = 0; + (a[15] => z[12]) = 0; + (a[16] => z[12]) = 0; + (a[17] => z[12]) = 0; + (a[18] => z[12]) = 0; + (a[19] => z[12]) = 0; + (b[0] => z[12]) = 0; + (b[1] => z[12]) = 0; + (b[2] => z[12]) = 0; + (b[3] => z[12]) = 0; + (b[4] => z[12]) = 0; + (b[5] => z[12]) = 0; + (b[6] => z[12]) = 0; + (b[7] => z[12]) = 0; + (b[8] => z[12]) = 0; + (b[9] => z[12]) = 0; + (b[10] => z[12]) = 0; + (b[11] => z[12]) = 0; + (b[12] => z[12]) = 0; + (b[13] => z[12]) = 0; + (b[14] => z[12]) = 0; + (b[15] => z[12]) = 0; + (b[16] => z[12]) = 0; + (b[17] => z[12]) = 0; + (a[0] => z[13]) = 0; + (a[1] => z[13]) = 0; + (a[2] => z[13]) = 0; + (a[3] => z[13]) = 0; + (a[4] => z[13]) = 0; + (a[5] => z[13]) = 0; + (a[6] => z[13]) = 0; + (a[7] => z[13]) = 0; + (a[8] => z[13]) = 0; + (a[9] => z[13]) = 0; + (a[10] => z[13]) = 0; + (a[11] => z[13]) = 0; + (a[12] => z[13]) = 0; + (a[13] => z[13]) = 0; + (a[14] => z[13]) = 0; + (a[15] => z[13]) = 0; + (a[16] => z[13]) = 0; + (a[17] => z[13]) = 0; + (a[18] => z[13]) = 0; + (a[19] => z[13]) = 0; + (b[0] => z[13]) = 0; + (b[1] => z[13]) = 0; + (b[2] => z[13]) = 0; + (b[3] => z[13]) = 0; + (b[4] => z[13]) = 0; + (b[5] => z[13]) = 0; + (b[6] => z[13]) = 0; + (b[7] => z[13]) = 0; + (b[8] => z[13]) = 0; + (b[9] => z[13]) = 0; + (b[10] => z[13]) = 0; + (b[11] => z[13]) = 0; + (b[12] => z[13]) = 0; + (b[13] => z[13]) = 0; + (b[14] => z[13]) = 0; + (b[15] => z[13]) = 0; + (b[16] => z[13]) = 0; + (b[17] => z[13]) = 0; + (a[0] => z[14]) = 0; + (a[1] => z[14]) = 0; + (a[2] => z[14]) = 0; + (a[3] => z[14]) = 0; + (a[4] => z[14]) = 0; + (a[5] => z[14]) = 0; + (a[6] => z[14]) = 0; + (a[7] => z[14]) = 0; + (a[8] => z[14]) = 0; + (a[9] => z[14]) = 0; + (a[10] => z[14]) = 0; + (a[11] => z[14]) = 0; + (a[12] => z[14]) = 0; + (a[13] => z[14]) = 0; + (a[14] => z[14]) = 0; + (a[15] => z[14]) = 0; + (a[16] => z[14]) = 0; + (a[17] => z[14]) = 0; + (a[18] => z[14]) = 0; + (a[19] => z[14]) = 0; + (b[0] => z[14]) = 0; + (b[1] => z[14]) = 0; + (b[2] => z[14]) = 0; + (b[3] => z[14]) = 0; + (b[4] => z[14]) = 0; + (b[5] => z[14]) = 0; + (b[6] => z[14]) = 0; + (b[7] => z[14]) = 0; + (b[8] => z[14]) = 0; + (b[9] => z[14]) = 0; + (b[10] => z[14]) = 0; + (b[11] => z[14]) = 0; + (b[12] => z[14]) = 0; + (b[13] => z[14]) = 0; + (b[14] => z[14]) = 0; + (b[15] => z[14]) = 0; + (b[16] => z[14]) = 0; + (b[17] => z[14]) = 0; + (a[0] => z[15]) = 0; + (a[1] => z[15]) = 0; + (a[2] => z[15]) = 0; + (a[3] => z[15]) = 0; + (a[4] => z[15]) = 0; + (a[5] => z[15]) = 0; + (a[6] => z[15]) = 0; + (a[7] => z[15]) = 0; + (a[8] => z[15]) = 0; + (a[9] => z[15]) = 0; + (a[10] => z[15]) = 0; + (a[11] => z[15]) = 0; + (a[12] => z[15]) = 0; + (a[13] => z[15]) = 0; + (a[14] => z[15]) = 0; + (a[15] => z[15]) = 0; + (a[16] => z[15]) = 0; + (a[17] => z[15]) = 0; + (a[18] => z[15]) = 0; + (a[19] => z[15]) = 0; + (b[0] => z[15]) = 0; + (b[1] => z[15]) = 0; + (b[2] => z[15]) = 0; + (b[3] => z[15]) = 0; + (b[4] => z[15]) = 0; + (b[5] => z[15]) = 0; + (b[6] => z[15]) = 0; + (b[7] => z[15]) = 0; + (b[8] => z[15]) = 0; + (b[9] => z[15]) = 0; + (b[10] => z[15]) = 0; + (b[11] => z[15]) = 0; + (b[12] => z[15]) = 0; + (b[13] => z[15]) = 0; + (b[14] => z[15]) = 0; + (b[15] => z[15]) = 0; + (b[16] => z[15]) = 0; + (b[17] => z[15]) = 0; + (a[0] => z[16]) = 0; + (a[1] => z[16]) = 0; + (a[2] => z[16]) = 0; + (a[3] => z[16]) = 0; + (a[4] => z[16]) = 0; + (a[5] => z[16]) = 0; + (a[6] => z[16]) = 0; + (a[7] => z[16]) = 0; + (a[8] => z[16]) = 0; + (a[9] => z[16]) = 0; + (a[10] => z[16]) = 0; + (a[11] => z[16]) = 0; + (a[12] => z[16]) = 0; + (a[13] => z[16]) = 0; + (a[14] => z[16]) = 0; + (a[15] => z[16]) = 0; + (a[16] => z[16]) = 0; + (a[17] => z[16]) = 0; + (a[18] => z[16]) = 0; + (a[19] => z[16]) = 0; + (b[0] => z[16]) = 0; + (b[1] => z[16]) = 0; + (b[2] => z[16]) = 0; + (b[3] => z[16]) = 0; + (b[4] => z[16]) = 0; + (b[5] => z[16]) = 0; + (b[6] => z[16]) = 0; + (b[7] => z[16]) = 0; + (b[8] => z[16]) = 0; + (b[9] => z[16]) = 0; + (b[10] => z[16]) = 0; + (b[11] => z[16]) = 0; + (b[12] => z[16]) = 0; + (b[13] => z[16]) = 0; + (b[14] => z[16]) = 0; + (b[15] => z[16]) = 0; + (b[16] => z[16]) = 0; + (b[17] => z[16]) = 0; + (a[0] => z[17]) = 0; + (a[1] => z[17]) = 0; + (a[2] => z[17]) = 0; + (a[3] => z[17]) = 0; + (a[4] => z[17]) = 0; + (a[5] => z[17]) = 0; + (a[6] => z[17]) = 0; + (a[7] => z[17]) = 0; + (a[8] => z[17]) = 0; + (a[9] => z[17]) = 0; + (a[10] => z[17]) = 0; + (a[11] => z[17]) = 0; + (a[12] => z[17]) = 0; + (a[13] => z[17]) = 0; + (a[14] => z[17]) = 0; + (a[15] => z[17]) = 0; + (a[16] => z[17]) = 0; + (a[17] => z[17]) = 0; + (a[18] => z[17]) = 0; + (a[19] => z[17]) = 0; + (b[0] => z[17]) = 0; + (b[1] => z[17]) = 0; + (b[2] => z[17]) = 0; + (b[3] => z[17]) = 0; + (b[4] => z[17]) = 0; + (b[5] => z[17]) = 0; + (b[6] => z[17]) = 0; + (b[7] => z[17]) = 0; + (b[8] => z[17]) = 0; + (b[9] => z[17]) = 0; + (b[10] => z[17]) = 0; + (b[11] => z[17]) = 0; + (b[12] => z[17]) = 0; + (b[13] => z[17]) = 0; + (b[14] => z[17]) = 0; + (b[15] => z[17]) = 0; + (b[16] => z[17]) = 0; + (b[17] => z[17]) = 0; + (a[0] => z[18]) = 0; + (a[1] => z[18]) = 0; + (a[2] => z[18]) = 0; + (a[3] => z[18]) = 0; + (a[4] => z[18]) = 0; + (a[5] => z[18]) = 0; + (a[6] => z[18]) = 0; + (a[7] => z[18]) = 0; + (a[8] => z[18]) = 0; + (a[9] => z[18]) = 0; + (a[10] => z[18]) = 0; + (a[11] => z[18]) = 0; + (a[12] => z[18]) = 0; + (a[13] => z[18]) = 0; + (a[14] => z[18]) = 0; + (a[15] => z[18]) = 0; + (a[16] => z[18]) = 0; + (a[17] => z[18]) = 0; + (a[18] => z[18]) = 0; + (a[19] => z[18]) = 0; + (b[0] => z[18]) = 0; + (b[1] => z[18]) = 0; + (b[2] => z[18]) = 0; + (b[3] => z[18]) = 0; + (b[4] => z[18]) = 0; + (b[5] => z[18]) = 0; + (b[6] => z[18]) = 0; + (b[7] => z[18]) = 0; + (b[8] => z[18]) = 0; + (b[9] => z[18]) = 0; + (b[10] => z[18]) = 0; + (b[11] => z[18]) = 0; + (b[12] => z[18]) = 0; + (b[13] => z[18]) = 0; + (b[14] => z[18]) = 0; + (b[15] => z[18]) = 0; + (b[16] => z[18]) = 0; + (b[17] => z[18]) = 0; + (a[0] => z[19]) = 0; + (a[1] => z[19]) = 0; + (a[2] => z[19]) = 0; + (a[3] => z[19]) = 0; + (a[4] => z[19]) = 0; + (a[5] => z[19]) = 0; + (a[6] => z[19]) = 0; + (a[7] => z[19]) = 0; + (a[8] => z[19]) = 0; + (a[9] => z[19]) = 0; + (a[10] => z[19]) = 0; + (a[11] => z[19]) = 0; + (a[12] => z[19]) = 0; + (a[13] => z[19]) = 0; + (a[14] => z[19]) = 0; + (a[15] => z[19]) = 0; + (a[16] => z[19]) = 0; + (a[17] => z[19]) = 0; + (a[18] => z[19]) = 0; + (a[19] => z[19]) = 0; + (b[0] => z[19]) = 0; + (b[1] => z[19]) = 0; + (b[2] => z[19]) = 0; + (b[3] => z[19]) = 0; + (b[4] => z[19]) = 0; + (b[5] => z[19]) = 0; + (b[6] => z[19]) = 0; + (b[7] => z[19]) = 0; + (b[8] => z[19]) = 0; + (b[9] => z[19]) = 0; + (b[10] => z[19]) = 0; + (b[11] => z[19]) = 0; + (b[12] => z[19]) = 0; + (b[13] => z[19]) = 0; + (b[14] => z[19]) = 0; + (b[15] => z[19]) = 0; + (b[16] => z[19]) = 0; + (b[17] => z[19]) = 0; + (a[0] => z[20]) = 0; + (a[1] => z[20]) = 0; + (a[2] => z[20]) = 0; + (a[3] => z[20]) = 0; + (a[4] => z[20]) = 0; + (a[5] => z[20]) = 0; + (a[6] => z[20]) = 0; + (a[7] => z[20]) = 0; + (a[8] => z[20]) = 0; + (a[9] => z[20]) = 0; + (a[10] => z[20]) = 0; + (a[11] => z[20]) = 0; + (a[12] => z[20]) = 0; + (a[13] => z[20]) = 0; + (a[14] => z[20]) = 0; + (a[15] => z[20]) = 0; + (a[16] => z[20]) = 0; + (a[17] => z[20]) = 0; + (a[18] => z[20]) = 0; + (a[19] => z[20]) = 0; + (b[0] => z[20]) = 0; + (b[1] => z[20]) = 0; + (b[2] => z[20]) = 0; + (b[3] => z[20]) = 0; + (b[4] => z[20]) = 0; + (b[5] => z[20]) = 0; + (b[6] => z[20]) = 0; + (b[7] => z[20]) = 0; + (b[8] => z[20]) = 0; + (b[9] => z[20]) = 0; + (b[10] => z[20]) = 0; + (b[11] => z[20]) = 0; + (b[12] => z[20]) = 0; + (b[13] => z[20]) = 0; + (b[14] => z[20]) = 0; + (b[15] => z[20]) = 0; + (b[16] => z[20]) = 0; + (b[17] => z[20]) = 0; + (a[0] => z[21]) = 0; + (a[1] => z[21]) = 0; + (a[2] => z[21]) = 0; + (a[3] => z[21]) = 0; + (a[4] => z[21]) = 0; + (a[5] => z[21]) = 0; + (a[6] => z[21]) = 0; + (a[7] => z[21]) = 0; + (a[8] => z[21]) = 0; + (a[9] => z[21]) = 0; + (a[10] => z[21]) = 0; + (a[11] => z[21]) = 0; + (a[12] => z[21]) = 0; + (a[13] => z[21]) = 0; + (a[14] => z[21]) = 0; + (a[15] => z[21]) = 0; + (a[16] => z[21]) = 0; + (a[17] => z[21]) = 0; + (a[18] => z[21]) = 0; + (a[19] => z[21]) = 0; + (b[0] => z[21]) = 0; + (b[1] => z[21]) = 0; + (b[2] => z[21]) = 0; + (b[3] => z[21]) = 0; + (b[4] => z[21]) = 0; + (b[5] => z[21]) = 0; + (b[6] => z[21]) = 0; + (b[7] => z[21]) = 0; + (b[8] => z[21]) = 0; + (b[9] => z[21]) = 0; + (b[10] => z[21]) = 0; + (b[11] => z[21]) = 0; + (b[12] => z[21]) = 0; + (b[13] => z[21]) = 0; + (b[14] => z[21]) = 0; + (b[15] => z[21]) = 0; + (b[16] => z[21]) = 0; + (b[17] => z[21]) = 0; + (a[0] => z[22]) = 0; + (a[1] => z[22]) = 0; + (a[2] => z[22]) = 0; + (a[3] => z[22]) = 0; + (a[4] => z[22]) = 0; + (a[5] => z[22]) = 0; + (a[6] => z[22]) = 0; + (a[7] => z[22]) = 0; + (a[8] => z[22]) = 0; + (a[9] => z[22]) = 0; + (a[10] => z[22]) = 0; + (a[11] => z[22]) = 0; + (a[12] => z[22]) = 0; + (a[13] => z[22]) = 0; + (a[14] => z[22]) = 0; + (a[15] => z[22]) = 0; + (a[16] => z[22]) = 0; + (a[17] => z[22]) = 0; + (a[18] => z[22]) = 0; + (a[19] => z[22]) = 0; + (b[0] => z[22]) = 0; + (b[1] => z[22]) = 0; + (b[2] => z[22]) = 0; + (b[3] => z[22]) = 0; + (b[4] => z[22]) = 0; + (b[5] => z[22]) = 0; + (b[6] => z[22]) = 0; + (b[7] => z[22]) = 0; + (b[8] => z[22]) = 0; + (b[9] => z[22]) = 0; + (b[10] => z[22]) = 0; + (b[11] => z[22]) = 0; + (b[12] => z[22]) = 0; + (b[13] => z[22]) = 0; + (b[14] => z[22]) = 0; + (b[15] => z[22]) = 0; + (b[16] => z[22]) = 0; + (b[17] => z[22]) = 0; + (a[0] => z[23]) = 0; + (a[1] => z[23]) = 0; + (a[2] => z[23]) = 0; + (a[3] => z[23]) = 0; + (a[4] => z[23]) = 0; + (a[5] => z[23]) = 0; + (a[6] => z[23]) = 0; + (a[7] => z[23]) = 0; + (a[8] => z[23]) = 0; + (a[9] => z[23]) = 0; + (a[10] => z[23]) = 0; + (a[11] => z[23]) = 0; + (a[12] => z[23]) = 0; + (a[13] => z[23]) = 0; + (a[14] => z[23]) = 0; + (a[15] => z[23]) = 0; + (a[16] => z[23]) = 0; + (a[17] => z[23]) = 0; + (a[18] => z[23]) = 0; + (a[19] => z[23]) = 0; + (b[0] => z[23]) = 0; + (b[1] => z[23]) = 0; + (b[2] => z[23]) = 0; + (b[3] => z[23]) = 0; + (b[4] => z[23]) = 0; + (b[5] => z[23]) = 0; + (b[6] => z[23]) = 0; + (b[7] => z[23]) = 0; + (b[8] => z[23]) = 0; + (b[9] => z[23]) = 0; + (b[10] => z[23]) = 0; + (b[11] => z[23]) = 0; + (b[12] => z[23]) = 0; + (b[13] => z[23]) = 0; + (b[14] => z[23]) = 0; + (b[15] => z[23]) = 0; + (b[16] => z[23]) = 0; + (b[17] => z[23]) = 0; + (a[0] => z[24]) = 0; + (a[1] => z[24]) = 0; + (a[2] => z[24]) = 0; + (a[3] => z[24]) = 0; + (a[4] => z[24]) = 0; + (a[5] => z[24]) = 0; + (a[6] => z[24]) = 0; + (a[7] => z[24]) = 0; + (a[8] => z[24]) = 0; + (a[9] => z[24]) = 0; + (a[10] => z[24]) = 0; + (a[11] => z[24]) = 0; + (a[12] => z[24]) = 0; + (a[13] => z[24]) = 0; + (a[14] => z[24]) = 0; + (a[15] => z[24]) = 0; + (a[16] => z[24]) = 0; + (a[17] => z[24]) = 0; + (a[18] => z[24]) = 0; + (a[19] => z[24]) = 0; + (b[0] => z[24]) = 0; + (b[1] => z[24]) = 0; + (b[2] => z[24]) = 0; + (b[3] => z[24]) = 0; + (b[4] => z[24]) = 0; + (b[5] => z[24]) = 0; + (b[6] => z[24]) = 0; + (b[7] => z[24]) = 0; + (b[8] => z[24]) = 0; + (b[9] => z[24]) = 0; + (b[10] => z[24]) = 0; + (b[11] => z[24]) = 0; + (b[12] => z[24]) = 0; + (b[13] => z[24]) = 0; + (b[14] => z[24]) = 0; + (b[15] => z[24]) = 0; + (b[16] => z[24]) = 0; + (b[17] => z[24]) = 0; + (a[0] => z[25]) = 0; + (a[1] => z[25]) = 0; + (a[2] => z[25]) = 0; + (a[3] => z[25]) = 0; + (a[4] => z[25]) = 0; + (a[5] => z[25]) = 0; + (a[6] => z[25]) = 0; + (a[7] => z[25]) = 0; + (a[8] => z[25]) = 0; + (a[9] => z[25]) = 0; + (a[10] => z[25]) = 0; + (a[11] => z[25]) = 0; + (a[12] => z[25]) = 0; + (a[13] => z[25]) = 0; + (a[14] => z[25]) = 0; + (a[15] => z[25]) = 0; + (a[16] => z[25]) = 0; + (a[17] => z[25]) = 0; + (a[18] => z[25]) = 0; + (a[19] => z[25]) = 0; + (b[0] => z[25]) = 0; + (b[1] => z[25]) = 0; + (b[2] => z[25]) = 0; + (b[3] => z[25]) = 0; + (b[4] => z[25]) = 0; + (b[5] => z[25]) = 0; + (b[6] => z[25]) = 0; + (b[7] => z[25]) = 0; + (b[8] => z[25]) = 0; + (b[9] => z[25]) = 0; + (b[10] => z[25]) = 0; + (b[11] => z[25]) = 0; + (b[12] => z[25]) = 0; + (b[13] => z[25]) = 0; + (b[14] => z[25]) = 0; + (b[15] => z[25]) = 0; + (b[16] => z[25]) = 0; + (b[17] => z[25]) = 0; + (a[0] => z[26]) = 0; + (a[1] => z[26]) = 0; + (a[2] => z[26]) = 0; + (a[3] => z[26]) = 0; + (a[4] => z[26]) = 0; + (a[5] => z[26]) = 0; + (a[6] => z[26]) = 0; + (a[7] => z[26]) = 0; + (a[8] => z[26]) = 0; + (a[9] => z[26]) = 0; + (a[10] => z[26]) = 0; + (a[11] => z[26]) = 0; + (a[12] => z[26]) = 0; + (a[13] => z[26]) = 0; + (a[14] => z[26]) = 0; + (a[15] => z[26]) = 0; + (a[16] => z[26]) = 0; + (a[17] => z[26]) = 0; + (a[18] => z[26]) = 0; + (a[19] => z[26]) = 0; + (b[0] => z[26]) = 0; + (b[1] => z[26]) = 0; + (b[2] => z[26]) = 0; + (b[3] => z[26]) = 0; + (b[4] => z[26]) = 0; + (b[5] => z[26]) = 0; + (b[6] => z[26]) = 0; + (b[7] => z[26]) = 0; + (b[8] => z[26]) = 0; + (b[9] => z[26]) = 0; + (b[10] => z[26]) = 0; + (b[11] => z[26]) = 0; + (b[12] => z[26]) = 0; + (b[13] => z[26]) = 0; + (b[14] => z[26]) = 0; + (b[15] => z[26]) = 0; + (b[16] => z[26]) = 0; + (b[17] => z[26]) = 0; + (a[0] => z[27]) = 0; + (a[1] => z[27]) = 0; + (a[2] => z[27]) = 0; + (a[3] => z[27]) = 0; + (a[4] => z[27]) = 0; + (a[5] => z[27]) = 0; + (a[6] => z[27]) = 0; + (a[7] => z[27]) = 0; + (a[8] => z[27]) = 0; + (a[9] => z[27]) = 0; + (a[10] => z[27]) = 0; + (a[11] => z[27]) = 0; + (a[12] => z[27]) = 0; + (a[13] => z[27]) = 0; + (a[14] => z[27]) = 0; + (a[15] => z[27]) = 0; + (a[16] => z[27]) = 0; + (a[17] => z[27]) = 0; + (a[18] => z[27]) = 0; + (a[19] => z[27]) = 0; + (b[0] => z[27]) = 0; + (b[1] => z[27]) = 0; + (b[2] => z[27]) = 0; + (b[3] => z[27]) = 0; + (b[4] => z[27]) = 0; + (b[5] => z[27]) = 0; + (b[6] => z[27]) = 0; + (b[7] => z[27]) = 0; + (b[8] => z[27]) = 0; + (b[9] => z[27]) = 0; + (b[10] => z[27]) = 0; + (b[11] => z[27]) = 0; + (b[12] => z[27]) = 0; + (b[13] => z[27]) = 0; + (b[14] => z[27]) = 0; + (b[15] => z[27]) = 0; + (b[16] => z[27]) = 0; + (b[17] => z[27]) = 0; + (a[0] => z[28]) = 0; + (a[1] => z[28]) = 0; + (a[2] => z[28]) = 0; + (a[3] => z[28]) = 0; + (a[4] => z[28]) = 0; + (a[5] => z[28]) = 0; + (a[6] => z[28]) = 0; + (a[7] => z[28]) = 0; + (a[8] => z[28]) = 0; + (a[9] => z[28]) = 0; + (a[10] => z[28]) = 0; + (a[11] => z[28]) = 0; + (a[12] => z[28]) = 0; + (a[13] => z[28]) = 0; + (a[14] => z[28]) = 0; + (a[15] => z[28]) = 0; + (a[16] => z[28]) = 0; + (a[17] => z[28]) = 0; + (a[18] => z[28]) = 0; + (a[19] => z[28]) = 0; + (b[0] => z[28]) = 0; + (b[1] => z[28]) = 0; + (b[2] => z[28]) = 0; + (b[3] => z[28]) = 0; + (b[4] => z[28]) = 0; + (b[5] => z[28]) = 0; + (b[6] => z[28]) = 0; + (b[7] => z[28]) = 0; + (b[8] => z[28]) = 0; + (b[9] => z[28]) = 0; + (b[10] => z[28]) = 0; + (b[11] => z[28]) = 0; + (b[12] => z[28]) = 0; + (b[13] => z[28]) = 0; + (b[14] => z[28]) = 0; + (b[15] => z[28]) = 0; + (b[16] => z[28]) = 0; + (b[17] => z[28]) = 0; + (a[0] => z[29]) = 0; + (a[1] => z[29]) = 0; + (a[2] => z[29]) = 0; + (a[3] => z[29]) = 0; + (a[4] => z[29]) = 0; + (a[5] => z[29]) = 0; + (a[6] => z[29]) = 0; + (a[7] => z[29]) = 0; + (a[8] => z[29]) = 0; + (a[9] => z[29]) = 0; + (a[10] => z[29]) = 0; + (a[11] => z[29]) = 0; + (a[12] => z[29]) = 0; + (a[13] => z[29]) = 0; + (a[14] => z[29]) = 0; + (a[15] => z[29]) = 0; + (a[16] => z[29]) = 0; + (a[17] => z[29]) = 0; + (a[18] => z[29]) = 0; + (a[19] => z[29]) = 0; + (b[0] => z[29]) = 0; + (b[1] => z[29]) = 0; + (b[2] => z[29]) = 0; + (b[3] => z[29]) = 0; + (b[4] => z[29]) = 0; + (b[5] => z[29]) = 0; + (b[6] => z[29]) = 0; + (b[7] => z[29]) = 0; + (b[8] => z[29]) = 0; + (b[9] => z[29]) = 0; + (b[10] => z[29]) = 0; + (b[11] => z[29]) = 0; + (b[12] => z[29]) = 0; + (b[13] => z[29]) = 0; + (b[14] => z[29]) = 0; + (b[15] => z[29]) = 0; + (b[16] => z[29]) = 0; + (b[17] => z[29]) = 0; + (a[0] => z[30]) = 0; + (a[1] => z[30]) = 0; + (a[2] => z[30]) = 0; + (a[3] => z[30]) = 0; + (a[4] => z[30]) = 0; + (a[5] => z[30]) = 0; + (a[6] => z[30]) = 0; + (a[7] => z[30]) = 0; + (a[8] => z[30]) = 0; + (a[9] => z[30]) = 0; + (a[10] => z[30]) = 0; + (a[11] => z[30]) = 0; + (a[12] => z[30]) = 0; + (a[13] => z[30]) = 0; + (a[14] => z[30]) = 0; + (a[15] => z[30]) = 0; + (a[16] => z[30]) = 0; + (a[17] => z[30]) = 0; + (a[18] => z[30]) = 0; + (a[19] => z[30]) = 0; + (b[0] => z[30]) = 0; + (b[1] => z[30]) = 0; + (b[2] => z[30]) = 0; + (b[3] => z[30]) = 0; + (b[4] => z[30]) = 0; + (b[5] => z[30]) = 0; + (b[6] => z[30]) = 0; + (b[7] => z[30]) = 0; + (b[8] => z[30]) = 0; + (b[9] => z[30]) = 0; + (b[10] => z[30]) = 0; + (b[11] => z[30]) = 0; + (b[12] => z[30]) = 0; + (b[13] => z[30]) = 0; + (b[14] => z[30]) = 0; + (b[15] => z[30]) = 0; + (b[16] => z[30]) = 0; + (b[17] => z[30]) = 0; + (a[0] => z[31]) = 0; + (a[1] => z[31]) = 0; + (a[2] => z[31]) = 0; + (a[3] => z[31]) = 0; + (a[4] => z[31]) = 0; + (a[5] => z[31]) = 0; + (a[6] => z[31]) = 0; + (a[7] => z[31]) = 0; + (a[8] => z[31]) = 0; + (a[9] => z[31]) = 0; + (a[10] => z[31]) = 0; + (a[11] => z[31]) = 0; + (a[12] => z[31]) = 0; + (a[13] => z[31]) = 0; + (a[14] => z[31]) = 0; + (a[15] => z[31]) = 0; + (a[16] => z[31]) = 0; + (a[17] => z[31]) = 0; + (a[18] => z[31]) = 0; + (a[19] => z[31]) = 0; + (b[0] => z[31]) = 0; + (b[1] => z[31]) = 0; + (b[2] => z[31]) = 0; + (b[3] => z[31]) = 0; + (b[4] => z[31]) = 0; + (b[5] => z[31]) = 0; + (b[6] => z[31]) = 0; + (b[7] => z[31]) = 0; + (b[8] => z[31]) = 0; + (b[9] => z[31]) = 0; + (b[10] => z[31]) = 0; + (b[11] => z[31]) = 0; + (b[12] => z[31]) = 0; + (b[13] => z[31]) = 0; + (b[14] => z[31]) = 0; + (b[15] => z[31]) = 0; + (b[16] => z[31]) = 0; + (b[17] => z[31]) = 0; + (a[0] => z[32]) = 0; + (a[1] => z[32]) = 0; + (a[2] => z[32]) = 0; + (a[3] => z[32]) = 0; + (a[4] => z[32]) = 0; + (a[5] => z[32]) = 0; + (a[6] => z[32]) = 0; + (a[7] => z[32]) = 0; + (a[8] => z[32]) = 0; + (a[9] => z[32]) = 0; + (a[10] => z[32]) = 0; + (a[11] => z[32]) = 0; + (a[12] => z[32]) = 0; + (a[13] => z[32]) = 0; + (a[14] => z[32]) = 0; + (a[15] => z[32]) = 0; + (a[16] => z[32]) = 0; + (a[17] => z[32]) = 0; + (a[18] => z[32]) = 0; + (a[19] => z[32]) = 0; + (b[0] => z[32]) = 0; + (b[1] => z[32]) = 0; + (b[2] => z[32]) = 0; + (b[3] => z[32]) = 0; + (b[4] => z[32]) = 0; + (b[5] => z[32]) = 0; + (b[6] => z[32]) = 0; + (b[7] => z[32]) = 0; + (b[8] => z[32]) = 0; + (b[9] => z[32]) = 0; + (b[10] => z[32]) = 0; + (b[11] => z[32]) = 0; + (b[12] => z[32]) = 0; + (b[13] => z[32]) = 0; + (b[14] => z[32]) = 0; + (b[15] => z[32]) = 0; + (b[16] => z[32]) = 0; + (b[17] => z[32]) = 0; + (a[0] => z[33]) = 0; + (a[1] => z[33]) = 0; + (a[2] => z[33]) = 0; + (a[3] => z[33]) = 0; + (a[4] => z[33]) = 0; + (a[5] => z[33]) = 0; + (a[6] => z[33]) = 0; + (a[7] => z[33]) = 0; + (a[8] => z[33]) = 0; + (a[9] => z[33]) = 0; + (a[10] => z[33]) = 0; + (a[11] => z[33]) = 0; + (a[12] => z[33]) = 0; + (a[13] => z[33]) = 0; + (a[14] => z[33]) = 0; + (a[15] => z[33]) = 0; + (a[16] => z[33]) = 0; + (a[17] => z[33]) = 0; + (a[18] => z[33]) = 0; + (a[19] => z[33]) = 0; + (b[0] => z[33]) = 0; + (b[1] => z[33]) = 0; + (b[2] => z[33]) = 0; + (b[3] => z[33]) = 0; + (b[4] => z[33]) = 0; + (b[5] => z[33]) = 0; + (b[6] => z[33]) = 0; + (b[7] => z[33]) = 0; + (b[8] => z[33]) = 0; + (b[9] => z[33]) = 0; + (b[10] => z[33]) = 0; + (b[11] => z[33]) = 0; + (b[12] => z[33]) = 0; + (b[13] => z[33]) = 0; + (b[14] => z[33]) = 0; + (b[15] => z[33]) = 0; + (b[16] => z[33]) = 0; + (b[17] => z[33]) = 0; + (a[0] => z[34]) = 0; + (a[1] => z[34]) = 0; + (a[2] => z[34]) = 0; + (a[3] => z[34]) = 0; + (a[4] => z[34]) = 0; + (a[5] => z[34]) = 0; + (a[6] => z[34]) = 0; + (a[7] => z[34]) = 0; + (a[8] => z[34]) = 0; + (a[9] => z[34]) = 0; + (a[10] => z[34]) = 0; + (a[11] => z[34]) = 0; + (a[12] => z[34]) = 0; + (a[13] => z[34]) = 0; + (a[14] => z[34]) = 0; + (a[15] => z[34]) = 0; + (a[16] => z[34]) = 0; + (a[17] => z[34]) = 0; + (a[18] => z[34]) = 0; + (a[19] => z[34]) = 0; + (b[0] => z[34]) = 0; + (b[1] => z[34]) = 0; + (b[2] => z[34]) = 0; + (b[3] => z[34]) = 0; + (b[4] => z[34]) = 0; + (b[5] => z[34]) = 0; + (b[6] => z[34]) = 0; + (b[7] => z[34]) = 0; + (b[8] => z[34]) = 0; + (b[9] => z[34]) = 0; + (b[10] => z[34]) = 0; + (b[11] => z[34]) = 0; + (b[12] => z[34]) = 0; + (b[13] => z[34]) = 0; + (b[14] => z[34]) = 0; + (b[15] => z[34]) = 0; + (b[16] => z[34]) = 0; + (b[17] => z[34]) = 0; + (a[0] => z[35]) = 0; + (a[1] => z[35]) = 0; + (a[2] => z[35]) = 0; + (a[3] => z[35]) = 0; + (a[4] => z[35]) = 0; + (a[5] => z[35]) = 0; + (a[6] => z[35]) = 0; + (a[7] => z[35]) = 0; + (a[8] => z[35]) = 0; + (a[9] => z[35]) = 0; + (a[10] => z[35]) = 0; + (a[11] => z[35]) = 0; + (a[12] => z[35]) = 0; + (a[13] => z[35]) = 0; + (a[14] => z[35]) = 0; + (a[15] => z[35]) = 0; + (a[16] => z[35]) = 0; + (a[17] => z[35]) = 0; + (a[18] => z[35]) = 0; + (a[19] => z[35]) = 0; + (b[0] => z[35]) = 0; + (b[1] => z[35]) = 0; + (b[2] => z[35]) = 0; + (b[3] => z[35]) = 0; + (b[4] => z[35]) = 0; + (b[5] => z[35]) = 0; + (b[6] => z[35]) = 0; + (b[7] => z[35]) = 0; + (b[8] => z[35]) = 0; + (b[9] => z[35]) = 0; + (b[10] => z[35]) = 0; + (b[11] => z[35]) = 0; + (b[12] => z[35]) = 0; + (b[13] => z[35]) = 0; + (b[14] => z[35]) = 0; + (b[15] => z[35]) = 0; + (b[16] => z[35]) = 0; + (b[17] => z[35]) = 0; + (a[0] => z[36]) = 0; + (a[1] => z[36]) = 0; + (a[2] => z[36]) = 0; + (a[3] => z[36]) = 0; + (a[4] => z[36]) = 0; + (a[5] => z[36]) = 0; + (a[6] => z[36]) = 0; + (a[7] => z[36]) = 0; + (a[8] => z[36]) = 0; + (a[9] => z[36]) = 0; + (a[10] => z[36]) = 0; + (a[11] => z[36]) = 0; + (a[12] => z[36]) = 0; + (a[13] => z[36]) = 0; + (a[14] => z[36]) = 0; + (a[15] => z[36]) = 0; + (a[16] => z[36]) = 0; + (a[17] => z[36]) = 0; + (a[18] => z[36]) = 0; + (a[19] => z[36]) = 0; + (b[0] => z[36]) = 0; + (b[1] => z[36]) = 0; + (b[2] => z[36]) = 0; + (b[3] => z[36]) = 0; + (b[4] => z[36]) = 0; + (b[5] => z[36]) = 0; + (b[6] => z[36]) = 0; + (b[7] => z[36]) = 0; + (b[8] => z[36]) = 0; + (b[9] => z[36]) = 0; + (b[10] => z[36]) = 0; + (b[11] => z[36]) = 0; + (b[12] => z[36]) = 0; + (b[13] => z[36]) = 0; + (b[14] => z[36]) = 0; + (b[15] => z[36]) = 0; + (b[16] => z[36]) = 0; + (b[17] => z[36]) = 0; + (a[0] => z[37]) = 0; + (a[1] => z[37]) = 0; + (a[2] => z[37]) = 0; + (a[3] => z[37]) = 0; + (a[4] => z[37]) = 0; + (a[5] => z[37]) = 0; + (a[6] => z[37]) = 0; + (a[7] => z[37]) = 0; + (a[8] => z[37]) = 0; + (a[9] => z[37]) = 0; + (a[10] => z[37]) = 0; + (a[11] => z[37]) = 0; + (a[12] => z[37]) = 0; + (a[13] => z[37]) = 0; + (a[14] => z[37]) = 0; + (a[15] => z[37]) = 0; + (a[16] => z[37]) = 0; + (a[17] => z[37]) = 0; + (a[18] => z[37]) = 0; + (a[19] => z[37]) = 0; + (b[0] => z[37]) = 0; + (b[1] => z[37]) = 0; + (b[2] => z[37]) = 0; + (b[3] => z[37]) = 0; + (b[4] => z[37]) = 0; + (b[5] => z[37]) = 0; + (b[6] => z[37]) = 0; + (b[7] => z[37]) = 0; + (b[8] => z[37]) = 0; + (b[9] => z[37]) = 0; + (b[10] => z[37]) = 0; + (b[11] => z[37]) = 0; + (b[12] => z[37]) = 0; + (b[13] => z[37]) = 0; + (b[14] => z[37]) = 0; + (b[15] => z[37]) = 0; + (b[16] => z[37]) = 0; + (b[17] => z[37]) = 0; + endspecify +`endif + +endmodule + +module QL_DSP2_MULT_REGIN ( // TODO: Name subject to change + input wire [19:0] a, + input wire [17:0] b, + output wire [37:0] z, + + (* clkbuf_sink *) + input wire clk, + input wire reset, + + input wire [2:0] feedback, + input wire unsigned_a, + input wire unsigned_b, + + input wire f_mode, + input wire [2:0] output_select, + input wire register_inputs +); + + parameter [79:0] MODE_BITS = 80'd0; + + localparam [19:0] COEFF_0 = MODE_BITS[19:0]; + localparam [19:0] COEFF_1 = MODE_BITS[39:20]; + localparam [19:0] COEFF_2 = MODE_BITS[59:40]; + localparam [19:0] COEFF_3 = MODE_BITS[79:60]; + + QL_DSP2 #( + .MODE_BITS({COEFF_3, COEFF_2, COEFF_1, COEFF_0}) + ) dsp ( + .a(a), + .b(b), + .acc_fir(6'b0), + .z(z), + .dly_b(), + + .f_mode(f_mode), + + .feedback(feedback), + .load_acc(1'b0), + + .unsigned_a(unsigned_a), + .unsigned_b(unsigned_b), + + .clk(clk), + .reset(reset), + + .output_select(output_select), // unregistered output: a * b (0) + .saturate_enable(1'b0), + .shift_right(6'b0), + .round(1'b0), + .subtract(1'b0), + .register_inputs(register_inputs) // registered inputs + ); + +`ifdef SDF_SIM + specify + (posedge clk => (z +: a)) = 0; + (posedge clk => (z +: b)) = 0; + $setuphold(posedge clk, a, 0, 0); + $setuphold(posedge clk, b, 0, 0); + $setuphold(posedge clk, feedback, 0, 0); + endspecify +`endif + +endmodule + +module QL_DSP2_MULT_REGOUT ( // TODO: Name subject to change + input wire [19:0] a, + input wire [17:0] b, + output wire [37:0] z, + + (* clkbuf_sink *) + input wire clk, + input wire reset, + + input wire [2:0] feedback, + input wire unsigned_a, + input wire unsigned_b, + input wire f_mode, + input wire [2:0] output_select, + input wire register_inputs +); + + parameter [79:0] MODE_BITS = 80'd0; + + localparam [19:0] COEFF_0 = MODE_BITS[19:0]; + localparam [19:0] COEFF_1 = MODE_BITS[39:20]; + localparam [19:0] COEFF_2 = MODE_BITS[59:40]; + localparam [19:0] COEFF_3 = MODE_BITS[79:60]; + + QL_DSP2 #( + .MODE_BITS({COEFF_3, COEFF_2, COEFF_1, COEFF_0}) + ) dsp ( + .a(a), + .b(b), + .acc_fir(6'b0), + .z(z), + .dly_b(), + + .f_mode(f_mode), + + .feedback(feedback), + .load_acc(1'b0), + + .unsigned_a(unsigned_a), + .unsigned_b(unsigned_b), + + .clk(clk), + .reset(reset), + + .output_select(output_select), // registered output: a * b (4) + .saturate_enable(1'b0), + .shift_right(6'b0), + .round(1'b0), + .subtract(1'b0), + .register_inputs(register_inputs) // unregistered inputs + ); + +`ifdef SDF_SIM + specify + (posedge clk => (z +: a)) = 0; + (posedge clk => (z +: b)) = 0; + $setuphold(posedge clk, a, 0, 0); + $setuphold(posedge clk, b, 0, 0); + $setuphold(posedge clk, feedback, 0, 0); + endspecify +`endif + +endmodule + +module QL_DSP2_MULT_REGIN_REGOUT ( // TODO: Name subject to change + input wire [19:0] a, + input wire [17:0] b, + output wire [37:0] z, + + (* clkbuf_sink *) + input wire clk, + input wire reset, + + input wire [2:0] feedback, + input wire unsigned_a, + input wire unsigned_b, + input wire f_mode, + input wire [2:0] output_select, + input wire register_inputs +); + + parameter [79:0] MODE_BITS = 80'd0; + + localparam [19:0] COEFF_0 = MODE_BITS[19:0]; + localparam [19:0] COEFF_1 = MODE_BITS[39:20]; + localparam [19:0] COEFF_2 = MODE_BITS[59:40]; + localparam [19:0] COEFF_3 = MODE_BITS[79:60]; + + QL_DSP2 #( + .MODE_BITS({COEFF_3, COEFF_2, COEFF_1, COEFF_0}) + ) dsp ( + .a(a), + .b(b), + .acc_fir(6'b0), + .z(z), + .dly_b(), + + .f_mode(f_mode), + + .feedback(feedback), + .load_acc(1'b0), + + .unsigned_a(unsigned_a), + .unsigned_b(unsigned_b), + + .clk(clk), + .reset(reset), + + .output_select(output_select), // registered output: a * b (4) + .saturate_enable(1'b0), + .shift_right(6'b0), + .round(1'b0), + .subtract(1'b0), + .register_inputs(register_inputs) // registered inputs + ); + +`ifdef SDF_SIM + specify + (posedge clk => (z +: a)) = 0; + (posedge clk => (z +: b)) = 0; + $setuphold(posedge clk, a, 0, 0); + $setuphold(posedge clk, b, 0, 0); + $setuphold(posedge clk, feedback, 0, 0); + endspecify +`endif + +endmodule + +module QL_DSP2_MULTADD ( + input wire [19:0] a, + input wire [17:0] b, + output wire [37:0] z, + + input wire reset, + + input wire [ 2:0] feedback, + input wire [ 5:0] acc_fir, + input wire load_acc, + input wire unsigned_a, + input wire unsigned_b, + + input wire f_mode, + input wire [ 2:0] output_select, + input wire saturate_enable, + input wire [ 5:0] shift_right, + input wire round, + input wire subtract, + input wire register_inputs +); + + parameter [79:0] MODE_BITS = 80'd0; + + localparam [19:0] COEFF_0 = MODE_BITS[19:0]; + localparam [19:0] COEFF_1 = MODE_BITS[39:20]; + localparam [19:0] COEFF_2 = MODE_BITS[59:40]; + localparam [19:0] COEFF_3 = MODE_BITS[79:60]; + + QL_DSP2 #( + .MODE_BITS({COEFF_3, COEFF_2, COEFF_1, COEFF_0}) + ) dsp ( + .a(a), + .b(b), + .dly_b(), + .z(z), + + .f_mode(f_mode), + + .feedback(feedback), + .acc_fir(acc_fir), + .load_acc(load_acc), + + .unsigned_a(unsigned_a), + .unsigned_b(unsigned_b), + + //.clk(1'b0), + .reset(reset), + + .output_select(output_select), // unregistered output: ACCin (2, 3) + .saturate_enable(saturate_enable), + .shift_right(shift_right), + .round(round), + .subtract(subtract), + .register_inputs(register_inputs) // unregistered inputs + ); + +`ifdef SDF_SIM + specify + (a[0] => z[0]) = 0; + (a[1] => z[0]) = 0; + (a[2] => z[0]) = 0; + (a[3] => z[0]) = 0; + (a[4] => z[0]) = 0; + (a[5] => z[0]) = 0; + (a[6] => z[0]) = 0; + (a[7] => z[0]) = 0; + (a[8] => z[0]) = 0; + (a[9] => z[0]) = 0; + (a[10] => z[0]) = 0; + (a[11] => z[0]) = 0; + (a[12] => z[0]) = 0; + (a[13] => z[0]) = 0; + (a[14] => z[0]) = 0; + (a[15] => z[0]) = 0; + (a[16] => z[0]) = 0; + (a[17] => z[0]) = 0; + (a[18] => z[0]) = 0; + (a[19] => z[0]) = 0; + (b[0] => z[0]) = 0; + (b[1] => z[0]) = 0; + (b[2] => z[0]) = 0; + (b[3] => z[0]) = 0; + (b[4] => z[0]) = 0; + (b[5] => z[0]) = 0; + (b[6] => z[0]) = 0; + (b[7] => z[0]) = 0; + (b[8] => z[0]) = 0; + (b[9] => z[0]) = 0; + (b[10] => z[0]) = 0; + (b[11] => z[0]) = 0; + (b[12] => z[0]) = 0; + (b[13] => z[0]) = 0; + (b[14] => z[0]) = 0; + (b[15] => z[0]) = 0; + (b[16] => z[0]) = 0; + (b[17] => z[0]) = 0; + (a[0] => z[1]) = 0; + (a[1] => z[1]) = 0; + (a[2] => z[1]) = 0; + (a[3] => z[1]) = 0; + (a[4] => z[1]) = 0; + (a[5] => z[1]) = 0; + (a[6] => z[1]) = 0; + (a[7] => z[1]) = 0; + (a[8] => z[1]) = 0; + (a[9] => z[1]) = 0; + (a[10] => z[1]) = 0; + (a[11] => z[1]) = 0; + (a[12] => z[1]) = 0; + (a[13] => z[1]) = 0; + (a[14] => z[1]) = 0; + (a[15] => z[1]) = 0; + (a[16] => z[1]) = 0; + (a[17] => z[1]) = 0; + (a[18] => z[1]) = 0; + (a[19] => z[1]) = 0; + (b[0] => z[1]) = 0; + (b[1] => z[1]) = 0; + (b[2] => z[1]) = 0; + (b[3] => z[1]) = 0; + (b[4] => z[1]) = 0; + (b[5] => z[1]) = 0; + (b[6] => z[1]) = 0; + (b[7] => z[1]) = 0; + (b[8] => z[1]) = 0; + (b[9] => z[1]) = 0; + (b[10] => z[1]) = 0; + (b[11] => z[1]) = 0; + (b[12] => z[1]) = 0; + (b[13] => z[1]) = 0; + (b[14] => z[1]) = 0; + (b[15] => z[1]) = 0; + (b[16] => z[1]) = 0; + (b[17] => z[1]) = 0; + (a[0] => z[2]) = 0; + (a[1] => z[2]) = 0; + (a[2] => z[2]) = 0; + (a[3] => z[2]) = 0; + (a[4] => z[2]) = 0; + (a[5] => z[2]) = 0; + (a[6] => z[2]) = 0; + (a[7] => z[2]) = 0; + (a[8] => z[2]) = 0; + (a[9] => z[2]) = 0; + (a[10] => z[2]) = 0; + (a[11] => z[2]) = 0; + (a[12] => z[2]) = 0; + (a[13] => z[2]) = 0; + (a[14] => z[2]) = 0; + (a[15] => z[2]) = 0; + (a[16] => z[2]) = 0; + (a[17] => z[2]) = 0; + (a[18] => z[2]) = 0; + (a[19] => z[2]) = 0; + (b[0] => z[2]) = 0; + (b[1] => z[2]) = 0; + (b[2] => z[2]) = 0; + (b[3] => z[2]) = 0; + (b[4] => z[2]) = 0; + (b[5] => z[2]) = 0; + (b[6] => z[2]) = 0; + (b[7] => z[2]) = 0; + (b[8] => z[2]) = 0; + (b[9] => z[2]) = 0; + (b[10] => z[2]) = 0; + (b[11] => z[2]) = 0; + (b[12] => z[2]) = 0; + (b[13] => z[2]) = 0; + (b[14] => z[2]) = 0; + (b[15] => z[2]) = 0; + (b[16] => z[2]) = 0; + (b[17] => z[2]) = 0; + (a[0] => z[3]) = 0; + (a[1] => z[3]) = 0; + (a[2] => z[3]) = 0; + (a[3] => z[3]) = 0; + (a[4] => z[3]) = 0; + (a[5] => z[3]) = 0; + (a[6] => z[3]) = 0; + (a[7] => z[3]) = 0; + (a[8] => z[3]) = 0; + (a[9] => z[3]) = 0; + (a[10] => z[3]) = 0; + (a[11] => z[3]) = 0; + (a[12] => z[3]) = 0; + (a[13] => z[3]) = 0; + (a[14] => z[3]) = 0; + (a[15] => z[3]) = 0; + (a[16] => z[3]) = 0; + (a[17] => z[3]) = 0; + (a[18] => z[3]) = 0; + (a[19] => z[3]) = 0; + (b[0] => z[3]) = 0; + (b[1] => z[3]) = 0; + (b[2] => z[3]) = 0; + (b[3] => z[3]) = 0; + (b[4] => z[3]) = 0; + (b[5] => z[3]) = 0; + (b[6] => z[3]) = 0; + (b[7] => z[3]) = 0; + (b[8] => z[3]) = 0; + (b[9] => z[3]) = 0; + (b[10] => z[3]) = 0; + (b[11] => z[3]) = 0; + (b[12] => z[3]) = 0; + (b[13] => z[3]) = 0; + (b[14] => z[3]) = 0; + (b[15] => z[3]) = 0; + (b[16] => z[3]) = 0; + (b[17] => z[3]) = 0; + (a[0] => z[4]) = 0; + (a[1] => z[4]) = 0; + (a[2] => z[4]) = 0; + (a[3] => z[4]) = 0; + (a[4] => z[4]) = 0; + (a[5] => z[4]) = 0; + (a[6] => z[4]) = 0; + (a[7] => z[4]) = 0; + (a[8] => z[4]) = 0; + (a[9] => z[4]) = 0; + (a[10] => z[4]) = 0; + (a[11] => z[4]) = 0; + (a[12] => z[4]) = 0; + (a[13] => z[4]) = 0; + (a[14] => z[4]) = 0; + (a[15] => z[4]) = 0; + (a[16] => z[4]) = 0; + (a[17] => z[4]) = 0; + (a[18] => z[4]) = 0; + (a[19] => z[4]) = 0; + (b[0] => z[4]) = 0; + (b[1] => z[4]) = 0; + (b[2] => z[4]) = 0; + (b[3] => z[4]) = 0; + (b[4] => z[4]) = 0; + (b[5] => z[4]) = 0; + (b[6] => z[4]) = 0; + (b[7] => z[4]) = 0; + (b[8] => z[4]) = 0; + (b[9] => z[4]) = 0; + (b[10] => z[4]) = 0; + (b[11] => z[4]) = 0; + (b[12] => z[4]) = 0; + (b[13] => z[4]) = 0; + (b[14] => z[4]) = 0; + (b[15] => z[4]) = 0; + (b[16] => z[4]) = 0; + (b[17] => z[4]) = 0; + (a[0] => z[5]) = 0; + (a[1] => z[5]) = 0; + (a[2] => z[5]) = 0; + (a[3] => z[5]) = 0; + (a[4] => z[5]) = 0; + (a[5] => z[5]) = 0; + (a[6] => z[5]) = 0; + (a[7] => z[5]) = 0; + (a[8] => z[5]) = 0; + (a[9] => z[5]) = 0; + (a[10] => z[5]) = 0; + (a[11] => z[5]) = 0; + (a[12] => z[5]) = 0; + (a[13] => z[5]) = 0; + (a[14] => z[5]) = 0; + (a[15] => z[5]) = 0; + (a[16] => z[5]) = 0; + (a[17] => z[5]) = 0; + (a[18] => z[5]) = 0; + (a[19] => z[5]) = 0; + (b[0] => z[5]) = 0; + (b[1] => z[5]) = 0; + (b[2] => z[5]) = 0; + (b[3] => z[5]) = 0; + (b[4] => z[5]) = 0; + (b[5] => z[5]) = 0; + (b[6] => z[5]) = 0; + (b[7] => z[5]) = 0; + (b[8] => z[5]) = 0; + (b[9] => z[5]) = 0; + (b[10] => z[5]) = 0; + (b[11] => z[5]) = 0; + (b[12] => z[5]) = 0; + (b[13] => z[5]) = 0; + (b[14] => z[5]) = 0; + (b[15] => z[5]) = 0; + (b[16] => z[5]) = 0; + (b[17] => z[5]) = 0; + (a[0] => z[6]) = 0; + (a[1] => z[6]) = 0; + (a[2] => z[6]) = 0; + (a[3] => z[6]) = 0; + (a[4] => z[6]) = 0; + (a[5] => z[6]) = 0; + (a[6] => z[6]) = 0; + (a[7] => z[6]) = 0; + (a[8] => z[6]) = 0; + (a[9] => z[6]) = 0; + (a[10] => z[6]) = 0; + (a[11] => z[6]) = 0; + (a[12] => z[6]) = 0; + (a[13] => z[6]) = 0; + (a[14] => z[6]) = 0; + (a[15] => z[6]) = 0; + (a[16] => z[6]) = 0; + (a[17] => z[6]) = 0; + (a[18] => z[6]) = 0; + (a[19] => z[6]) = 0; + (b[0] => z[6]) = 0; + (b[1] => z[6]) = 0; + (b[2] => z[6]) = 0; + (b[3] => z[6]) = 0; + (b[4] => z[6]) = 0; + (b[5] => z[6]) = 0; + (b[6] => z[6]) = 0; + (b[7] => z[6]) = 0; + (b[8] => z[6]) = 0; + (b[9] => z[6]) = 0; + (b[10] => z[6]) = 0; + (b[11] => z[6]) = 0; + (b[12] => z[6]) = 0; + (b[13] => z[6]) = 0; + (b[14] => z[6]) = 0; + (b[15] => z[6]) = 0; + (b[16] => z[6]) = 0; + (b[17] => z[6]) = 0; + (a[0] => z[7]) = 0; + (a[1] => z[7]) = 0; + (a[2] => z[7]) = 0; + (a[3] => z[7]) = 0; + (a[4] => z[7]) = 0; + (a[5] => z[7]) = 0; + (a[6] => z[7]) = 0; + (a[7] => z[7]) = 0; + (a[8] => z[7]) = 0; + (a[9] => z[7]) = 0; + (a[10] => z[7]) = 0; + (a[11] => z[7]) = 0; + (a[12] => z[7]) = 0; + (a[13] => z[7]) = 0; + (a[14] => z[7]) = 0; + (a[15] => z[7]) = 0; + (a[16] => z[7]) = 0; + (a[17] => z[7]) = 0; + (a[18] => z[7]) = 0; + (a[19] => z[7]) = 0; + (b[0] => z[7]) = 0; + (b[1] => z[7]) = 0; + (b[2] => z[7]) = 0; + (b[3] => z[7]) = 0; + (b[4] => z[7]) = 0; + (b[5] => z[7]) = 0; + (b[6] => z[7]) = 0; + (b[7] => z[7]) = 0; + (b[8] => z[7]) = 0; + (b[9] => z[7]) = 0; + (b[10] => z[7]) = 0; + (b[11] => z[7]) = 0; + (b[12] => z[7]) = 0; + (b[13] => z[7]) = 0; + (b[14] => z[7]) = 0; + (b[15] => z[7]) = 0; + (b[16] => z[7]) = 0; + (b[17] => z[7]) = 0; + (a[0] => z[8]) = 0; + (a[1] => z[8]) = 0; + (a[2] => z[8]) = 0; + (a[3] => z[8]) = 0; + (a[4] => z[8]) = 0; + (a[5] => z[8]) = 0; + (a[6] => z[8]) = 0; + (a[7] => z[8]) = 0; + (a[8] => z[8]) = 0; + (a[9] => z[8]) = 0; + (a[10] => z[8]) = 0; + (a[11] => z[8]) = 0; + (a[12] => z[8]) = 0; + (a[13] => z[8]) = 0; + (a[14] => z[8]) = 0; + (a[15] => z[8]) = 0; + (a[16] => z[8]) = 0; + (a[17] => z[8]) = 0; + (a[18] => z[8]) = 0; + (a[19] => z[8]) = 0; + (b[0] => z[8]) = 0; + (b[1] => z[8]) = 0; + (b[2] => z[8]) = 0; + (b[3] => z[8]) = 0; + (b[4] => z[8]) = 0; + (b[5] => z[8]) = 0; + (b[6] => z[8]) = 0; + (b[7] => z[8]) = 0; + (b[8] => z[8]) = 0; + (b[9] => z[8]) = 0; + (b[10] => z[8]) = 0; + (b[11] => z[8]) = 0; + (b[12] => z[8]) = 0; + (b[13] => z[8]) = 0; + (b[14] => z[8]) = 0; + (b[15] => z[8]) = 0; + (b[16] => z[8]) = 0; + (b[17] => z[8]) = 0; + (a[0] => z[9]) = 0; + (a[1] => z[9]) = 0; + (a[2] => z[9]) = 0; + (a[3] => z[9]) = 0; + (a[4] => z[9]) = 0; + (a[5] => z[9]) = 0; + (a[6] => z[9]) = 0; + (a[7] => z[9]) = 0; + (a[8] => z[9]) = 0; + (a[9] => z[9]) = 0; + (a[10] => z[9]) = 0; + (a[11] => z[9]) = 0; + (a[12] => z[9]) = 0; + (a[13] => z[9]) = 0; + (a[14] => z[9]) = 0; + (a[15] => z[9]) = 0; + (a[16] => z[9]) = 0; + (a[17] => z[9]) = 0; + (a[18] => z[9]) = 0; + (a[19] => z[9]) = 0; + (b[0] => z[9]) = 0; + (b[1] => z[9]) = 0; + (b[2] => z[9]) = 0; + (b[3] => z[9]) = 0; + (b[4] => z[9]) = 0; + (b[5] => z[9]) = 0; + (b[6] => z[9]) = 0; + (b[7] => z[9]) = 0; + (b[8] => z[9]) = 0; + (b[9] => z[9]) = 0; + (b[10] => z[9]) = 0; + (b[11] => z[9]) = 0; + (b[12] => z[9]) = 0; + (b[13] => z[9]) = 0; + (b[14] => z[9]) = 0; + (b[15] => z[9]) = 0; + (b[16] => z[9]) = 0; + (b[17] => z[9]) = 0; + (a[0] => z[10]) = 0; + (a[1] => z[10]) = 0; + (a[2] => z[10]) = 0; + (a[3] => z[10]) = 0; + (a[4] => z[10]) = 0; + (a[5] => z[10]) = 0; + (a[6] => z[10]) = 0; + (a[7] => z[10]) = 0; + (a[8] => z[10]) = 0; + (a[9] => z[10]) = 0; + (a[10] => z[10]) = 0; + (a[11] => z[10]) = 0; + (a[12] => z[10]) = 0; + (a[13] => z[10]) = 0; + (a[14] => z[10]) = 0; + (a[15] => z[10]) = 0; + (a[16] => z[10]) = 0; + (a[17] => z[10]) = 0; + (a[18] => z[10]) = 0; + (a[19] => z[10]) = 0; + (b[0] => z[10]) = 0; + (b[1] => z[10]) = 0; + (b[2] => z[10]) = 0; + (b[3] => z[10]) = 0; + (b[4] => z[10]) = 0; + (b[5] => z[10]) = 0; + (b[6] => z[10]) = 0; + (b[7] => z[10]) = 0; + (b[8] => z[10]) = 0; + (b[9] => z[10]) = 0; + (b[10] => z[10]) = 0; + (b[11] => z[10]) = 0; + (b[12] => z[10]) = 0; + (b[13] => z[10]) = 0; + (b[14] => z[10]) = 0; + (b[15] => z[10]) = 0; + (b[16] => z[10]) = 0; + (b[17] => z[10]) = 0; + (a[0] => z[11]) = 0; + (a[1] => z[11]) = 0; + (a[2] => z[11]) = 0; + (a[3] => z[11]) = 0; + (a[4] => z[11]) = 0; + (a[5] => z[11]) = 0; + (a[6] => z[11]) = 0; + (a[7] => z[11]) = 0; + (a[8] => z[11]) = 0; + (a[9] => z[11]) = 0; + (a[10] => z[11]) = 0; + (a[11] => z[11]) = 0; + (a[12] => z[11]) = 0; + (a[13] => z[11]) = 0; + (a[14] => z[11]) = 0; + (a[15] => z[11]) = 0; + (a[16] => z[11]) = 0; + (a[17] => z[11]) = 0; + (a[18] => z[11]) = 0; + (a[19] => z[11]) = 0; + (b[0] => z[11]) = 0; + (b[1] => z[11]) = 0; + (b[2] => z[11]) = 0; + (b[3] => z[11]) = 0; + (b[4] => z[11]) = 0; + (b[5] => z[11]) = 0; + (b[6] => z[11]) = 0; + (b[7] => z[11]) = 0; + (b[8] => z[11]) = 0; + (b[9] => z[11]) = 0; + (b[10] => z[11]) = 0; + (b[11] => z[11]) = 0; + (b[12] => z[11]) = 0; + (b[13] => z[11]) = 0; + (b[14] => z[11]) = 0; + (b[15] => z[11]) = 0; + (b[16] => z[11]) = 0; + (b[17] => z[11]) = 0; + (a[0] => z[12]) = 0; + (a[1] => z[12]) = 0; + (a[2] => z[12]) = 0; + (a[3] => z[12]) = 0; + (a[4] => z[12]) = 0; + (a[5] => z[12]) = 0; + (a[6] => z[12]) = 0; + (a[7] => z[12]) = 0; + (a[8] => z[12]) = 0; + (a[9] => z[12]) = 0; + (a[10] => z[12]) = 0; + (a[11] => z[12]) = 0; + (a[12] => z[12]) = 0; + (a[13] => z[12]) = 0; + (a[14] => z[12]) = 0; + (a[15] => z[12]) = 0; + (a[16] => z[12]) = 0; + (a[17] => z[12]) = 0; + (a[18] => z[12]) = 0; + (a[19] => z[12]) = 0; + (b[0] => z[12]) = 0; + (b[1] => z[12]) = 0; + (b[2] => z[12]) = 0; + (b[3] => z[12]) = 0; + (b[4] => z[12]) = 0; + (b[5] => z[12]) = 0; + (b[6] => z[12]) = 0; + (b[7] => z[12]) = 0; + (b[8] => z[12]) = 0; + (b[9] => z[12]) = 0; + (b[10] => z[12]) = 0; + (b[11] => z[12]) = 0; + (b[12] => z[12]) = 0; + (b[13] => z[12]) = 0; + (b[14] => z[12]) = 0; + (b[15] => z[12]) = 0; + (b[16] => z[12]) = 0; + (b[17] => z[12]) = 0; + (a[0] => z[13]) = 0; + (a[1] => z[13]) = 0; + (a[2] => z[13]) = 0; + (a[3] => z[13]) = 0; + (a[4] => z[13]) = 0; + (a[5] => z[13]) = 0; + (a[6] => z[13]) = 0; + (a[7] => z[13]) = 0; + (a[8] => z[13]) = 0; + (a[9] => z[13]) = 0; + (a[10] => z[13]) = 0; + (a[11] => z[13]) = 0; + (a[12] => z[13]) = 0; + (a[13] => z[13]) = 0; + (a[14] => z[13]) = 0; + (a[15] => z[13]) = 0; + (a[16] => z[13]) = 0; + (a[17] => z[13]) = 0; + (a[18] => z[13]) = 0; + (a[19] => z[13]) = 0; + (b[0] => z[13]) = 0; + (b[1] => z[13]) = 0; + (b[2] => z[13]) = 0; + (b[3] => z[13]) = 0; + (b[4] => z[13]) = 0; + (b[5] => z[13]) = 0; + (b[6] => z[13]) = 0; + (b[7] => z[13]) = 0; + (b[8] => z[13]) = 0; + (b[9] => z[13]) = 0; + (b[10] => z[13]) = 0; + (b[11] => z[13]) = 0; + (b[12] => z[13]) = 0; + (b[13] => z[13]) = 0; + (b[14] => z[13]) = 0; + (b[15] => z[13]) = 0; + (b[16] => z[13]) = 0; + (b[17] => z[13]) = 0; + (a[0] => z[14]) = 0; + (a[1] => z[14]) = 0; + (a[2] => z[14]) = 0; + (a[3] => z[14]) = 0; + (a[4] => z[14]) = 0; + (a[5] => z[14]) = 0; + (a[6] => z[14]) = 0; + (a[7] => z[14]) = 0; + (a[8] => z[14]) = 0; + (a[9] => z[14]) = 0; + (a[10] => z[14]) = 0; + (a[11] => z[14]) = 0; + (a[12] => z[14]) = 0; + (a[13] => z[14]) = 0; + (a[14] => z[14]) = 0; + (a[15] => z[14]) = 0; + (a[16] => z[14]) = 0; + (a[17] => z[14]) = 0; + (a[18] => z[14]) = 0; + (a[19] => z[14]) = 0; + (b[0] => z[14]) = 0; + (b[1] => z[14]) = 0; + (b[2] => z[14]) = 0; + (b[3] => z[14]) = 0; + (b[4] => z[14]) = 0; + (b[5] => z[14]) = 0; + (b[6] => z[14]) = 0; + (b[7] => z[14]) = 0; + (b[8] => z[14]) = 0; + (b[9] => z[14]) = 0; + (b[10] => z[14]) = 0; + (b[11] => z[14]) = 0; + (b[12] => z[14]) = 0; + (b[13] => z[14]) = 0; + (b[14] => z[14]) = 0; + (b[15] => z[14]) = 0; + (b[16] => z[14]) = 0; + (b[17] => z[14]) = 0; + (a[0] => z[15]) = 0; + (a[1] => z[15]) = 0; + (a[2] => z[15]) = 0; + (a[3] => z[15]) = 0; + (a[4] => z[15]) = 0; + (a[5] => z[15]) = 0; + (a[6] => z[15]) = 0; + (a[7] => z[15]) = 0; + (a[8] => z[15]) = 0; + (a[9] => z[15]) = 0; + (a[10] => z[15]) = 0; + (a[11] => z[15]) = 0; + (a[12] => z[15]) = 0; + (a[13] => z[15]) = 0; + (a[14] => z[15]) = 0; + (a[15] => z[15]) = 0; + (a[16] => z[15]) = 0; + (a[17] => z[15]) = 0; + (a[18] => z[15]) = 0; + (a[19] => z[15]) = 0; + (b[0] => z[15]) = 0; + (b[1] => z[15]) = 0; + (b[2] => z[15]) = 0; + (b[3] => z[15]) = 0; + (b[4] => z[15]) = 0; + (b[5] => z[15]) = 0; + (b[6] => z[15]) = 0; + (b[7] => z[15]) = 0; + (b[8] => z[15]) = 0; + (b[9] => z[15]) = 0; + (b[10] => z[15]) = 0; + (b[11] => z[15]) = 0; + (b[12] => z[15]) = 0; + (b[13] => z[15]) = 0; + (b[14] => z[15]) = 0; + (b[15] => z[15]) = 0; + (b[16] => z[15]) = 0; + (b[17] => z[15]) = 0; + (a[0] => z[16]) = 0; + (a[1] => z[16]) = 0; + (a[2] => z[16]) = 0; + (a[3] => z[16]) = 0; + (a[4] => z[16]) = 0; + (a[5] => z[16]) = 0; + (a[6] => z[16]) = 0; + (a[7] => z[16]) = 0; + (a[8] => z[16]) = 0; + (a[9] => z[16]) = 0; + (a[10] => z[16]) = 0; + (a[11] => z[16]) = 0; + (a[12] => z[16]) = 0; + (a[13] => z[16]) = 0; + (a[14] => z[16]) = 0; + (a[15] => z[16]) = 0; + (a[16] => z[16]) = 0; + (a[17] => z[16]) = 0; + (a[18] => z[16]) = 0; + (a[19] => z[16]) = 0; + (b[0] => z[16]) = 0; + (b[1] => z[16]) = 0; + (b[2] => z[16]) = 0; + (b[3] => z[16]) = 0; + (b[4] => z[16]) = 0; + (b[5] => z[16]) = 0; + (b[6] => z[16]) = 0; + (b[7] => z[16]) = 0; + (b[8] => z[16]) = 0; + (b[9] => z[16]) = 0; + (b[10] => z[16]) = 0; + (b[11] => z[16]) = 0; + (b[12] => z[16]) = 0; + (b[13] => z[16]) = 0; + (b[14] => z[16]) = 0; + (b[15] => z[16]) = 0; + (b[16] => z[16]) = 0; + (b[17] => z[16]) = 0; + (a[0] => z[17]) = 0; + (a[1] => z[17]) = 0; + (a[2] => z[17]) = 0; + (a[3] => z[17]) = 0; + (a[4] => z[17]) = 0; + (a[5] => z[17]) = 0; + (a[6] => z[17]) = 0; + (a[7] => z[17]) = 0; + (a[8] => z[17]) = 0; + (a[9] => z[17]) = 0; + (a[10] => z[17]) = 0; + (a[11] => z[17]) = 0; + (a[12] => z[17]) = 0; + (a[13] => z[17]) = 0; + (a[14] => z[17]) = 0; + (a[15] => z[17]) = 0; + (a[16] => z[17]) = 0; + (a[17] => z[17]) = 0; + (a[18] => z[17]) = 0; + (a[19] => z[17]) = 0; + (b[0] => z[17]) = 0; + (b[1] => z[17]) = 0; + (b[2] => z[17]) = 0; + (b[3] => z[17]) = 0; + (b[4] => z[17]) = 0; + (b[5] => z[17]) = 0; + (b[6] => z[17]) = 0; + (b[7] => z[17]) = 0; + (b[8] => z[17]) = 0; + (b[9] => z[17]) = 0; + (b[10] => z[17]) = 0; + (b[11] => z[17]) = 0; + (b[12] => z[17]) = 0; + (b[13] => z[17]) = 0; + (b[14] => z[17]) = 0; + (b[15] => z[17]) = 0; + (b[16] => z[17]) = 0; + (b[17] => z[17]) = 0; + (a[0] => z[18]) = 0; + (a[1] => z[18]) = 0; + (a[2] => z[18]) = 0; + (a[3] => z[18]) = 0; + (a[4] => z[18]) = 0; + (a[5] => z[18]) = 0; + (a[6] => z[18]) = 0; + (a[7] => z[18]) = 0; + (a[8] => z[18]) = 0; + (a[9] => z[18]) = 0; + (a[10] => z[18]) = 0; + (a[11] => z[18]) = 0; + (a[12] => z[18]) = 0; + (a[13] => z[18]) = 0; + (a[14] => z[18]) = 0; + (a[15] => z[18]) = 0; + (a[16] => z[18]) = 0; + (a[17] => z[18]) = 0; + (a[18] => z[18]) = 0; + (a[19] => z[18]) = 0; + (b[0] => z[18]) = 0; + (b[1] => z[18]) = 0; + (b[2] => z[18]) = 0; + (b[3] => z[18]) = 0; + (b[4] => z[18]) = 0; + (b[5] => z[18]) = 0; + (b[6] => z[18]) = 0; + (b[7] => z[18]) = 0; + (b[8] => z[18]) = 0; + (b[9] => z[18]) = 0; + (b[10] => z[18]) = 0; + (b[11] => z[18]) = 0; + (b[12] => z[18]) = 0; + (b[13] => z[18]) = 0; + (b[14] => z[18]) = 0; + (b[15] => z[18]) = 0; + (b[16] => z[18]) = 0; + (b[17] => z[18]) = 0; + (a[0] => z[19]) = 0; + (a[1] => z[19]) = 0; + (a[2] => z[19]) = 0; + (a[3] => z[19]) = 0; + (a[4] => z[19]) = 0; + (a[5] => z[19]) = 0; + (a[6] => z[19]) = 0; + (a[7] => z[19]) = 0; + (a[8] => z[19]) = 0; + (a[9] => z[19]) = 0; + (a[10] => z[19]) = 0; + (a[11] => z[19]) = 0; + (a[12] => z[19]) = 0; + (a[13] => z[19]) = 0; + (a[14] => z[19]) = 0; + (a[15] => z[19]) = 0; + (a[16] => z[19]) = 0; + (a[17] => z[19]) = 0; + (a[18] => z[19]) = 0; + (a[19] => z[19]) = 0; + (b[0] => z[19]) = 0; + (b[1] => z[19]) = 0; + (b[2] => z[19]) = 0; + (b[3] => z[19]) = 0; + (b[4] => z[19]) = 0; + (b[5] => z[19]) = 0; + (b[6] => z[19]) = 0; + (b[7] => z[19]) = 0; + (b[8] => z[19]) = 0; + (b[9] => z[19]) = 0; + (b[10] => z[19]) = 0; + (b[11] => z[19]) = 0; + (b[12] => z[19]) = 0; + (b[13] => z[19]) = 0; + (b[14] => z[19]) = 0; + (b[15] => z[19]) = 0; + (b[16] => z[19]) = 0; + (b[17] => z[19]) = 0; + (a[0] => z[20]) = 0; + (a[1] => z[20]) = 0; + (a[2] => z[20]) = 0; + (a[3] => z[20]) = 0; + (a[4] => z[20]) = 0; + (a[5] => z[20]) = 0; + (a[6] => z[20]) = 0; + (a[7] => z[20]) = 0; + (a[8] => z[20]) = 0; + (a[9] => z[20]) = 0; + (a[10] => z[20]) = 0; + (a[11] => z[20]) = 0; + (a[12] => z[20]) = 0; + (a[13] => z[20]) = 0; + (a[14] => z[20]) = 0; + (a[15] => z[20]) = 0; + (a[16] => z[20]) = 0; + (a[17] => z[20]) = 0; + (a[18] => z[20]) = 0; + (a[19] => z[20]) = 0; + (b[0] => z[20]) = 0; + (b[1] => z[20]) = 0; + (b[2] => z[20]) = 0; + (b[3] => z[20]) = 0; + (b[4] => z[20]) = 0; + (b[5] => z[20]) = 0; + (b[6] => z[20]) = 0; + (b[7] => z[20]) = 0; + (b[8] => z[20]) = 0; + (b[9] => z[20]) = 0; + (b[10] => z[20]) = 0; + (b[11] => z[20]) = 0; + (b[12] => z[20]) = 0; + (b[13] => z[20]) = 0; + (b[14] => z[20]) = 0; + (b[15] => z[20]) = 0; + (b[16] => z[20]) = 0; + (b[17] => z[20]) = 0; + (a[0] => z[21]) = 0; + (a[1] => z[21]) = 0; + (a[2] => z[21]) = 0; + (a[3] => z[21]) = 0; + (a[4] => z[21]) = 0; + (a[5] => z[21]) = 0; + (a[6] => z[21]) = 0; + (a[7] => z[21]) = 0; + (a[8] => z[21]) = 0; + (a[9] => z[21]) = 0; + (a[10] => z[21]) = 0; + (a[11] => z[21]) = 0; + (a[12] => z[21]) = 0; + (a[13] => z[21]) = 0; + (a[14] => z[21]) = 0; + (a[15] => z[21]) = 0; + (a[16] => z[21]) = 0; + (a[17] => z[21]) = 0; + (a[18] => z[21]) = 0; + (a[19] => z[21]) = 0; + (b[0] => z[21]) = 0; + (b[1] => z[21]) = 0; + (b[2] => z[21]) = 0; + (b[3] => z[21]) = 0; + (b[4] => z[21]) = 0; + (b[5] => z[21]) = 0; + (b[6] => z[21]) = 0; + (b[7] => z[21]) = 0; + (b[8] => z[21]) = 0; + (b[9] => z[21]) = 0; + (b[10] => z[21]) = 0; + (b[11] => z[21]) = 0; + (b[12] => z[21]) = 0; + (b[13] => z[21]) = 0; + (b[14] => z[21]) = 0; + (b[15] => z[21]) = 0; + (b[16] => z[21]) = 0; + (b[17] => z[21]) = 0; + (a[0] => z[22]) = 0; + (a[1] => z[22]) = 0; + (a[2] => z[22]) = 0; + (a[3] => z[22]) = 0; + (a[4] => z[22]) = 0; + (a[5] => z[22]) = 0; + (a[6] => z[22]) = 0; + (a[7] => z[22]) = 0; + (a[8] => z[22]) = 0; + (a[9] => z[22]) = 0; + (a[10] => z[22]) = 0; + (a[11] => z[22]) = 0; + (a[12] => z[22]) = 0; + (a[13] => z[22]) = 0; + (a[14] => z[22]) = 0; + (a[15] => z[22]) = 0; + (a[16] => z[22]) = 0; + (a[17] => z[22]) = 0; + (a[18] => z[22]) = 0; + (a[19] => z[22]) = 0; + (b[0] => z[22]) = 0; + (b[1] => z[22]) = 0; + (b[2] => z[22]) = 0; + (b[3] => z[22]) = 0; + (b[4] => z[22]) = 0; + (b[5] => z[22]) = 0; + (b[6] => z[22]) = 0; + (b[7] => z[22]) = 0; + (b[8] => z[22]) = 0; + (b[9] => z[22]) = 0; + (b[10] => z[22]) = 0; + (b[11] => z[22]) = 0; + (b[12] => z[22]) = 0; + (b[13] => z[22]) = 0; + (b[14] => z[22]) = 0; + (b[15] => z[22]) = 0; + (b[16] => z[22]) = 0; + (b[17] => z[22]) = 0; + (a[0] => z[23]) = 0; + (a[1] => z[23]) = 0; + (a[2] => z[23]) = 0; + (a[3] => z[23]) = 0; + (a[4] => z[23]) = 0; + (a[5] => z[23]) = 0; + (a[6] => z[23]) = 0; + (a[7] => z[23]) = 0; + (a[8] => z[23]) = 0; + (a[9] => z[23]) = 0; + (a[10] => z[23]) = 0; + (a[11] => z[23]) = 0; + (a[12] => z[23]) = 0; + (a[13] => z[23]) = 0; + (a[14] => z[23]) = 0; + (a[15] => z[23]) = 0; + (a[16] => z[23]) = 0; + (a[17] => z[23]) = 0; + (a[18] => z[23]) = 0; + (a[19] => z[23]) = 0; + (b[0] => z[23]) = 0; + (b[1] => z[23]) = 0; + (b[2] => z[23]) = 0; + (b[3] => z[23]) = 0; + (b[4] => z[23]) = 0; + (b[5] => z[23]) = 0; + (b[6] => z[23]) = 0; + (b[7] => z[23]) = 0; + (b[8] => z[23]) = 0; + (b[9] => z[23]) = 0; + (b[10] => z[23]) = 0; + (b[11] => z[23]) = 0; + (b[12] => z[23]) = 0; + (b[13] => z[23]) = 0; + (b[14] => z[23]) = 0; + (b[15] => z[23]) = 0; + (b[16] => z[23]) = 0; + (b[17] => z[23]) = 0; + (a[0] => z[24]) = 0; + (a[1] => z[24]) = 0; + (a[2] => z[24]) = 0; + (a[3] => z[24]) = 0; + (a[4] => z[24]) = 0; + (a[5] => z[24]) = 0; + (a[6] => z[24]) = 0; + (a[7] => z[24]) = 0; + (a[8] => z[24]) = 0; + (a[9] => z[24]) = 0; + (a[10] => z[24]) = 0; + (a[11] => z[24]) = 0; + (a[12] => z[24]) = 0; + (a[13] => z[24]) = 0; + (a[14] => z[24]) = 0; + (a[15] => z[24]) = 0; + (a[16] => z[24]) = 0; + (a[17] => z[24]) = 0; + (a[18] => z[24]) = 0; + (a[19] => z[24]) = 0; + (b[0] => z[24]) = 0; + (b[1] => z[24]) = 0; + (b[2] => z[24]) = 0; + (b[3] => z[24]) = 0; + (b[4] => z[24]) = 0; + (b[5] => z[24]) = 0; + (b[6] => z[24]) = 0; + (b[7] => z[24]) = 0; + (b[8] => z[24]) = 0; + (b[9] => z[24]) = 0; + (b[10] => z[24]) = 0; + (b[11] => z[24]) = 0; + (b[12] => z[24]) = 0; + (b[13] => z[24]) = 0; + (b[14] => z[24]) = 0; + (b[15] => z[24]) = 0; + (b[16] => z[24]) = 0; + (b[17] => z[24]) = 0; + (a[0] => z[25]) = 0; + (a[1] => z[25]) = 0; + (a[2] => z[25]) = 0; + (a[3] => z[25]) = 0; + (a[4] => z[25]) = 0; + (a[5] => z[25]) = 0; + (a[6] => z[25]) = 0; + (a[7] => z[25]) = 0; + (a[8] => z[25]) = 0; + (a[9] => z[25]) = 0; + (a[10] => z[25]) = 0; + (a[11] => z[25]) = 0; + (a[12] => z[25]) = 0; + (a[13] => z[25]) = 0; + (a[14] => z[25]) = 0; + (a[15] => z[25]) = 0; + (a[16] => z[25]) = 0; + (a[17] => z[25]) = 0; + (a[18] => z[25]) = 0; + (a[19] => z[25]) = 0; + (b[0] => z[25]) = 0; + (b[1] => z[25]) = 0; + (b[2] => z[25]) = 0; + (b[3] => z[25]) = 0; + (b[4] => z[25]) = 0; + (b[5] => z[25]) = 0; + (b[6] => z[25]) = 0; + (b[7] => z[25]) = 0; + (b[8] => z[25]) = 0; + (b[9] => z[25]) = 0; + (b[10] => z[25]) = 0; + (b[11] => z[25]) = 0; + (b[12] => z[25]) = 0; + (b[13] => z[25]) = 0; + (b[14] => z[25]) = 0; + (b[15] => z[25]) = 0; + (b[16] => z[25]) = 0; + (b[17] => z[25]) = 0; + (a[0] => z[26]) = 0; + (a[1] => z[26]) = 0; + (a[2] => z[26]) = 0; + (a[3] => z[26]) = 0; + (a[4] => z[26]) = 0; + (a[5] => z[26]) = 0; + (a[6] => z[26]) = 0; + (a[7] => z[26]) = 0; + (a[8] => z[26]) = 0; + (a[9] => z[26]) = 0; + (a[10] => z[26]) = 0; + (a[11] => z[26]) = 0; + (a[12] => z[26]) = 0; + (a[13] => z[26]) = 0; + (a[14] => z[26]) = 0; + (a[15] => z[26]) = 0; + (a[16] => z[26]) = 0; + (a[17] => z[26]) = 0; + (a[18] => z[26]) = 0; + (a[19] => z[26]) = 0; + (b[0] => z[26]) = 0; + (b[1] => z[26]) = 0; + (b[2] => z[26]) = 0; + (b[3] => z[26]) = 0; + (b[4] => z[26]) = 0; + (b[5] => z[26]) = 0; + (b[6] => z[26]) = 0; + (b[7] => z[26]) = 0; + (b[8] => z[26]) = 0; + (b[9] => z[26]) = 0; + (b[10] => z[26]) = 0; + (b[11] => z[26]) = 0; + (b[12] => z[26]) = 0; + (b[13] => z[26]) = 0; + (b[14] => z[26]) = 0; + (b[15] => z[26]) = 0; + (b[16] => z[26]) = 0; + (b[17] => z[26]) = 0; + (a[0] => z[27]) = 0; + (a[1] => z[27]) = 0; + (a[2] => z[27]) = 0; + (a[3] => z[27]) = 0; + (a[4] => z[27]) = 0; + (a[5] => z[27]) = 0; + (a[6] => z[27]) = 0; + (a[7] => z[27]) = 0; + (a[8] => z[27]) = 0; + (a[9] => z[27]) = 0; + (a[10] => z[27]) = 0; + (a[11] => z[27]) = 0; + (a[12] => z[27]) = 0; + (a[13] => z[27]) = 0; + (a[14] => z[27]) = 0; + (a[15] => z[27]) = 0; + (a[16] => z[27]) = 0; + (a[17] => z[27]) = 0; + (a[18] => z[27]) = 0; + (a[19] => z[27]) = 0; + (b[0] => z[27]) = 0; + (b[1] => z[27]) = 0; + (b[2] => z[27]) = 0; + (b[3] => z[27]) = 0; + (b[4] => z[27]) = 0; + (b[5] => z[27]) = 0; + (b[6] => z[27]) = 0; + (b[7] => z[27]) = 0; + (b[8] => z[27]) = 0; + (b[9] => z[27]) = 0; + (b[10] => z[27]) = 0; + (b[11] => z[27]) = 0; + (b[12] => z[27]) = 0; + (b[13] => z[27]) = 0; + (b[14] => z[27]) = 0; + (b[15] => z[27]) = 0; + (b[16] => z[27]) = 0; + (b[17] => z[27]) = 0; + (a[0] => z[28]) = 0; + (a[1] => z[28]) = 0; + (a[2] => z[28]) = 0; + (a[3] => z[28]) = 0; + (a[4] => z[28]) = 0; + (a[5] => z[28]) = 0; + (a[6] => z[28]) = 0; + (a[7] => z[28]) = 0; + (a[8] => z[28]) = 0; + (a[9] => z[28]) = 0; + (a[10] => z[28]) = 0; + (a[11] => z[28]) = 0; + (a[12] => z[28]) = 0; + (a[13] => z[28]) = 0; + (a[14] => z[28]) = 0; + (a[15] => z[28]) = 0; + (a[16] => z[28]) = 0; + (a[17] => z[28]) = 0; + (a[18] => z[28]) = 0; + (a[19] => z[28]) = 0; + (b[0] => z[28]) = 0; + (b[1] => z[28]) = 0; + (b[2] => z[28]) = 0; + (b[3] => z[28]) = 0; + (b[4] => z[28]) = 0; + (b[5] => z[28]) = 0; + (b[6] => z[28]) = 0; + (b[7] => z[28]) = 0; + (b[8] => z[28]) = 0; + (b[9] => z[28]) = 0; + (b[10] => z[28]) = 0; + (b[11] => z[28]) = 0; + (b[12] => z[28]) = 0; + (b[13] => z[28]) = 0; + (b[14] => z[28]) = 0; + (b[15] => z[28]) = 0; + (b[16] => z[28]) = 0; + (b[17] => z[28]) = 0; + (a[0] => z[29]) = 0; + (a[1] => z[29]) = 0; + (a[2] => z[29]) = 0; + (a[3] => z[29]) = 0; + (a[4] => z[29]) = 0; + (a[5] => z[29]) = 0; + (a[6] => z[29]) = 0; + (a[7] => z[29]) = 0; + (a[8] => z[29]) = 0; + (a[9] => z[29]) = 0; + (a[10] => z[29]) = 0; + (a[11] => z[29]) = 0; + (a[12] => z[29]) = 0; + (a[13] => z[29]) = 0; + (a[14] => z[29]) = 0; + (a[15] => z[29]) = 0; + (a[16] => z[29]) = 0; + (a[17] => z[29]) = 0; + (a[18] => z[29]) = 0; + (a[19] => z[29]) = 0; + (b[0] => z[29]) = 0; + (b[1] => z[29]) = 0; + (b[2] => z[29]) = 0; + (b[3] => z[29]) = 0; + (b[4] => z[29]) = 0; + (b[5] => z[29]) = 0; + (b[6] => z[29]) = 0; + (b[7] => z[29]) = 0; + (b[8] => z[29]) = 0; + (b[9] => z[29]) = 0; + (b[10] => z[29]) = 0; + (b[11] => z[29]) = 0; + (b[12] => z[29]) = 0; + (b[13] => z[29]) = 0; + (b[14] => z[29]) = 0; + (b[15] => z[29]) = 0; + (b[16] => z[29]) = 0; + (b[17] => z[29]) = 0; + (a[0] => z[30]) = 0; + (a[1] => z[30]) = 0; + (a[2] => z[30]) = 0; + (a[3] => z[30]) = 0; + (a[4] => z[30]) = 0; + (a[5] => z[30]) = 0; + (a[6] => z[30]) = 0; + (a[7] => z[30]) = 0; + (a[8] => z[30]) = 0; + (a[9] => z[30]) = 0; + (a[10] => z[30]) = 0; + (a[11] => z[30]) = 0; + (a[12] => z[30]) = 0; + (a[13] => z[30]) = 0; + (a[14] => z[30]) = 0; + (a[15] => z[30]) = 0; + (a[16] => z[30]) = 0; + (a[17] => z[30]) = 0; + (a[18] => z[30]) = 0; + (a[19] => z[30]) = 0; + (b[0] => z[30]) = 0; + (b[1] => z[30]) = 0; + (b[2] => z[30]) = 0; + (b[3] => z[30]) = 0; + (b[4] => z[30]) = 0; + (b[5] => z[30]) = 0; + (b[6] => z[30]) = 0; + (b[7] => z[30]) = 0; + (b[8] => z[30]) = 0; + (b[9] => z[30]) = 0; + (b[10] => z[30]) = 0; + (b[11] => z[30]) = 0; + (b[12] => z[30]) = 0; + (b[13] => z[30]) = 0; + (b[14] => z[30]) = 0; + (b[15] => z[30]) = 0; + (b[16] => z[30]) = 0; + (b[17] => z[30]) = 0; + (a[0] => z[31]) = 0; + (a[1] => z[31]) = 0; + (a[2] => z[31]) = 0; + (a[3] => z[31]) = 0; + (a[4] => z[31]) = 0; + (a[5] => z[31]) = 0; + (a[6] => z[31]) = 0; + (a[7] => z[31]) = 0; + (a[8] => z[31]) = 0; + (a[9] => z[31]) = 0; + (a[10] => z[31]) = 0; + (a[11] => z[31]) = 0; + (a[12] => z[31]) = 0; + (a[13] => z[31]) = 0; + (a[14] => z[31]) = 0; + (a[15] => z[31]) = 0; + (a[16] => z[31]) = 0; + (a[17] => z[31]) = 0; + (a[18] => z[31]) = 0; + (a[19] => z[31]) = 0; + (b[0] => z[31]) = 0; + (b[1] => z[31]) = 0; + (b[2] => z[31]) = 0; + (b[3] => z[31]) = 0; + (b[4] => z[31]) = 0; + (b[5] => z[31]) = 0; + (b[6] => z[31]) = 0; + (b[7] => z[31]) = 0; + (b[8] => z[31]) = 0; + (b[9] => z[31]) = 0; + (b[10] => z[31]) = 0; + (b[11] => z[31]) = 0; + (b[12] => z[31]) = 0; + (b[13] => z[31]) = 0; + (b[14] => z[31]) = 0; + (b[15] => z[31]) = 0; + (b[16] => z[31]) = 0; + (b[17] => z[31]) = 0; + (a[0] => z[32]) = 0; + (a[1] => z[32]) = 0; + (a[2] => z[32]) = 0; + (a[3] => z[32]) = 0; + (a[4] => z[32]) = 0; + (a[5] => z[32]) = 0; + (a[6] => z[32]) = 0; + (a[7] => z[32]) = 0; + (a[8] => z[32]) = 0; + (a[9] => z[32]) = 0; + (a[10] => z[32]) = 0; + (a[11] => z[32]) = 0; + (a[12] => z[32]) = 0; + (a[13] => z[32]) = 0; + (a[14] => z[32]) = 0; + (a[15] => z[32]) = 0; + (a[16] => z[32]) = 0; + (a[17] => z[32]) = 0; + (a[18] => z[32]) = 0; + (a[19] => z[32]) = 0; + (b[0] => z[32]) = 0; + (b[1] => z[32]) = 0; + (b[2] => z[32]) = 0; + (b[3] => z[32]) = 0; + (b[4] => z[32]) = 0; + (b[5] => z[32]) = 0; + (b[6] => z[32]) = 0; + (b[7] => z[32]) = 0; + (b[8] => z[32]) = 0; + (b[9] => z[32]) = 0; + (b[10] => z[32]) = 0; + (b[11] => z[32]) = 0; + (b[12] => z[32]) = 0; + (b[13] => z[32]) = 0; + (b[14] => z[32]) = 0; + (b[15] => z[32]) = 0; + (b[16] => z[32]) = 0; + (b[17] => z[32]) = 0; + (a[0] => z[33]) = 0; + (a[1] => z[33]) = 0; + (a[2] => z[33]) = 0; + (a[3] => z[33]) = 0; + (a[4] => z[33]) = 0; + (a[5] => z[33]) = 0; + (a[6] => z[33]) = 0; + (a[7] => z[33]) = 0; + (a[8] => z[33]) = 0; + (a[9] => z[33]) = 0; + (a[10] => z[33]) = 0; + (a[11] => z[33]) = 0; + (a[12] => z[33]) = 0; + (a[13] => z[33]) = 0; + (a[14] => z[33]) = 0; + (a[15] => z[33]) = 0; + (a[16] => z[33]) = 0; + (a[17] => z[33]) = 0; + (a[18] => z[33]) = 0; + (a[19] => z[33]) = 0; + (b[0] => z[33]) = 0; + (b[1] => z[33]) = 0; + (b[2] => z[33]) = 0; + (b[3] => z[33]) = 0; + (b[4] => z[33]) = 0; + (b[5] => z[33]) = 0; + (b[6] => z[33]) = 0; + (b[7] => z[33]) = 0; + (b[8] => z[33]) = 0; + (b[9] => z[33]) = 0; + (b[10] => z[33]) = 0; + (b[11] => z[33]) = 0; + (b[12] => z[33]) = 0; + (b[13] => z[33]) = 0; + (b[14] => z[33]) = 0; + (b[15] => z[33]) = 0; + (b[16] => z[33]) = 0; + (b[17] => z[33]) = 0; + (a[0] => z[34]) = 0; + (a[1] => z[34]) = 0; + (a[2] => z[34]) = 0; + (a[3] => z[34]) = 0; + (a[4] => z[34]) = 0; + (a[5] => z[34]) = 0; + (a[6] => z[34]) = 0; + (a[7] => z[34]) = 0; + (a[8] => z[34]) = 0; + (a[9] => z[34]) = 0; + (a[10] => z[34]) = 0; + (a[11] => z[34]) = 0; + (a[12] => z[34]) = 0; + (a[13] => z[34]) = 0; + (a[14] => z[34]) = 0; + (a[15] => z[34]) = 0; + (a[16] => z[34]) = 0; + (a[17] => z[34]) = 0; + (a[18] => z[34]) = 0; + (a[19] => z[34]) = 0; + (b[0] => z[34]) = 0; + (b[1] => z[34]) = 0; + (b[2] => z[34]) = 0; + (b[3] => z[34]) = 0; + (b[4] => z[34]) = 0; + (b[5] => z[34]) = 0; + (b[6] => z[34]) = 0; + (b[7] => z[34]) = 0; + (b[8] => z[34]) = 0; + (b[9] => z[34]) = 0; + (b[10] => z[34]) = 0; + (b[11] => z[34]) = 0; + (b[12] => z[34]) = 0; + (b[13] => z[34]) = 0; + (b[14] => z[34]) = 0; + (b[15] => z[34]) = 0; + (b[16] => z[34]) = 0; + (b[17] => z[34]) = 0; + (a[0] => z[35]) = 0; + (a[1] => z[35]) = 0; + (a[2] => z[35]) = 0; + (a[3] => z[35]) = 0; + (a[4] => z[35]) = 0; + (a[5] => z[35]) = 0; + (a[6] => z[35]) = 0; + (a[7] => z[35]) = 0; + (a[8] => z[35]) = 0; + (a[9] => z[35]) = 0; + (a[10] => z[35]) = 0; + (a[11] => z[35]) = 0; + (a[12] => z[35]) = 0; + (a[13] => z[35]) = 0; + (a[14] => z[35]) = 0; + (a[15] => z[35]) = 0; + (a[16] => z[35]) = 0; + (a[17] => z[35]) = 0; + (a[18] => z[35]) = 0; + (a[19] => z[35]) = 0; + (b[0] => z[35]) = 0; + (b[1] => z[35]) = 0; + (b[2] => z[35]) = 0; + (b[3] => z[35]) = 0; + (b[4] => z[35]) = 0; + (b[5] => z[35]) = 0; + (b[6] => z[35]) = 0; + (b[7] => z[35]) = 0; + (b[8] => z[35]) = 0; + (b[9] => z[35]) = 0; + (b[10] => z[35]) = 0; + (b[11] => z[35]) = 0; + (b[12] => z[35]) = 0; + (b[13] => z[35]) = 0; + (b[14] => z[35]) = 0; + (b[15] => z[35]) = 0; + (b[16] => z[35]) = 0; + (b[17] => z[35]) = 0; + (a[0] => z[36]) = 0; + (a[1] => z[36]) = 0; + (a[2] => z[36]) = 0; + (a[3] => z[36]) = 0; + (a[4] => z[36]) = 0; + (a[5] => z[36]) = 0; + (a[6] => z[36]) = 0; + (a[7] => z[36]) = 0; + (a[8] => z[36]) = 0; + (a[9] => z[36]) = 0; + (a[10] => z[36]) = 0; + (a[11] => z[36]) = 0; + (a[12] => z[36]) = 0; + (a[13] => z[36]) = 0; + (a[14] => z[36]) = 0; + (a[15] => z[36]) = 0; + (a[16] => z[36]) = 0; + (a[17] => z[36]) = 0; + (a[18] => z[36]) = 0; + (a[19] => z[36]) = 0; + (b[0] => z[36]) = 0; + (b[1] => z[36]) = 0; + (b[2] => z[36]) = 0; + (b[3] => z[36]) = 0; + (b[4] => z[36]) = 0; + (b[5] => z[36]) = 0; + (b[6] => z[36]) = 0; + (b[7] => z[36]) = 0; + (b[8] => z[36]) = 0; + (b[9] => z[36]) = 0; + (b[10] => z[36]) = 0; + (b[11] => z[36]) = 0; + (b[12] => z[36]) = 0; + (b[13] => z[36]) = 0; + (b[14] => z[36]) = 0; + (b[15] => z[36]) = 0; + (b[16] => z[36]) = 0; + (b[17] => z[36]) = 0; + (a[0] => z[37]) = 0; + (a[1] => z[37]) = 0; + (a[2] => z[37]) = 0; + (a[3] => z[37]) = 0; + (a[4] => z[37]) = 0; + (a[5] => z[37]) = 0; + (a[6] => z[37]) = 0; + (a[7] => z[37]) = 0; + (a[8] => z[37]) = 0; + (a[9] => z[37]) = 0; + (a[10] => z[37]) = 0; + (a[11] => z[37]) = 0; + (a[12] => z[37]) = 0; + (a[13] => z[37]) = 0; + (a[14] => z[37]) = 0; + (a[15] => z[37]) = 0; + (a[16] => z[37]) = 0; + (a[17] => z[37]) = 0; + (a[18] => z[37]) = 0; + (a[19] => z[37]) = 0; + (b[0] => z[37]) = 0; + (b[1] => z[37]) = 0; + (b[2] => z[37]) = 0; + (b[3] => z[37]) = 0; + (b[4] => z[37]) = 0; + (b[5] => z[37]) = 0; + (b[6] => z[37]) = 0; + (b[7] => z[37]) = 0; + (b[8] => z[37]) = 0; + (b[9] => z[37]) = 0; + (b[10] => z[37]) = 0; + (b[11] => z[37]) = 0; + (b[12] => z[37]) = 0; + (b[13] => z[37]) = 0; + (b[14] => z[37]) = 0; + (b[15] => z[37]) = 0; + (b[16] => z[37]) = 0; + (b[17] => z[37]) = 0; + (subtract => z[0]) = 0; + (subtract => z[1]) = 0; + (subtract => z[2]) = 0; + (subtract => z[3]) = 0; + (subtract => z[4]) = 0; + (subtract => z[5]) = 0; + (subtract => z[6]) = 0; + (subtract => z[7]) = 0; + (subtract => z[8]) = 0; + (subtract => z[9]) = 0; + (subtract => z[10]) = 0; + (subtract => z[11]) = 0; + (subtract => z[12]) = 0; + (subtract => z[13]) = 0; + (subtract => z[14]) = 0; + (subtract => z[15]) = 0; + (subtract => z[16]) = 0; + (subtract => z[17]) = 0; + (subtract => z[18]) = 0; + (subtract => z[19]) = 0; + (subtract => z[20]) = 0; + (subtract => z[21]) = 0; + (subtract => z[22]) = 0; + (subtract => z[23]) = 0; + (subtract => z[24]) = 0; + (subtract => z[25]) = 0; + (subtract => z[26]) = 0; + (subtract => z[27]) = 0; + (subtract => z[28]) = 0; + (subtract => z[29]) = 0; + (subtract => z[30]) = 0; + (subtract => z[31]) = 0; + (subtract => z[32]) = 0; + (subtract => z[33]) = 0; + (subtract => z[34]) = 0; + (subtract => z[35]) = 0; + (subtract => z[36]) = 0; + (subtract => z[37]) = 0; + (acc_fir[0] => z[0]) = 0; + (acc_fir[1] => z[0]) = 0; + (acc_fir[2] => z[0]) = 0; + (acc_fir[3] => z[0]) = 0; + (acc_fir[4] => z[0]) = 0; + (acc_fir[5] => z[0]) = 0; + (acc_fir[0] => z[1]) = 0; + (acc_fir[1] => z[1]) = 0; + (acc_fir[2] => z[1]) = 0; + (acc_fir[3] => z[1]) = 0; + (acc_fir[4] => z[1]) = 0; + (acc_fir[5] => z[1]) = 0; + (acc_fir[0] => z[2]) = 0; + (acc_fir[1] => z[2]) = 0; + (acc_fir[2] => z[2]) = 0; + (acc_fir[3] => z[2]) = 0; + (acc_fir[4] => z[2]) = 0; + (acc_fir[5] => z[2]) = 0; + (acc_fir[0] => z[3]) = 0; + (acc_fir[1] => z[3]) = 0; + (acc_fir[2] => z[3]) = 0; + (acc_fir[3] => z[3]) = 0; + (acc_fir[4] => z[3]) = 0; + (acc_fir[5] => z[3]) = 0; + (acc_fir[0] => z[4]) = 0; + (acc_fir[1] => z[4]) = 0; + (acc_fir[2] => z[4]) = 0; + (acc_fir[3] => z[4]) = 0; + (acc_fir[4] => z[4]) = 0; + (acc_fir[5] => z[4]) = 0; + (acc_fir[0] => z[5]) = 0; + (acc_fir[1] => z[5]) = 0; + (acc_fir[2] => z[5]) = 0; + (acc_fir[3] => z[5]) = 0; + (acc_fir[4] => z[5]) = 0; + (acc_fir[5] => z[5]) = 0; + (acc_fir[0] => z[6]) = 0; + (acc_fir[1] => z[6]) = 0; + (acc_fir[2] => z[6]) = 0; + (acc_fir[3] => z[6]) = 0; + (acc_fir[4] => z[6]) = 0; + (acc_fir[5] => z[6]) = 0; + (acc_fir[0] => z[7]) = 0; + (acc_fir[1] => z[7]) = 0; + (acc_fir[2] => z[7]) = 0; + (acc_fir[3] => z[7]) = 0; + (acc_fir[4] => z[7]) = 0; + (acc_fir[5] => z[7]) = 0; + (acc_fir[0] => z[8]) = 0; + (acc_fir[1] => z[8]) = 0; + (acc_fir[2] => z[8]) = 0; + (acc_fir[3] => z[8]) = 0; + (acc_fir[4] => z[8]) = 0; + (acc_fir[5] => z[8]) = 0; + (acc_fir[0] => z[9]) = 0; + (acc_fir[1] => z[9]) = 0; + (acc_fir[2] => z[9]) = 0; + (acc_fir[3] => z[9]) = 0; + (acc_fir[4] => z[9]) = 0; + (acc_fir[5] => z[9]) = 0; + (acc_fir[0] => z[10]) = 0; + (acc_fir[1] => z[10]) = 0; + (acc_fir[2] => z[10]) = 0; + (acc_fir[3] => z[10]) = 0; + (acc_fir[4] => z[10]) = 0; + (acc_fir[5] => z[10]) = 0; + (acc_fir[0] => z[11]) = 0; + (acc_fir[1] => z[11]) = 0; + (acc_fir[2] => z[11]) = 0; + (acc_fir[3] => z[11]) = 0; + (acc_fir[4] => z[11]) = 0; + (acc_fir[5] => z[11]) = 0; + (acc_fir[0] => z[12]) = 0; + (acc_fir[1] => z[12]) = 0; + (acc_fir[2] => z[12]) = 0; + (acc_fir[3] => z[12]) = 0; + (acc_fir[4] => z[12]) = 0; + (acc_fir[5] => z[12]) = 0; + (acc_fir[0] => z[13]) = 0; + (acc_fir[1] => z[13]) = 0; + (acc_fir[2] => z[13]) = 0; + (acc_fir[3] => z[13]) = 0; + (acc_fir[4] => z[13]) = 0; + (acc_fir[5] => z[13]) = 0; + (acc_fir[0] => z[14]) = 0; + (acc_fir[1] => z[14]) = 0; + (acc_fir[2] => z[14]) = 0; + (acc_fir[3] => z[14]) = 0; + (acc_fir[4] => z[14]) = 0; + (acc_fir[5] => z[14]) = 0; + (acc_fir[0] => z[15]) = 0; + (acc_fir[1] => z[15]) = 0; + (acc_fir[2] => z[15]) = 0; + (acc_fir[3] => z[15]) = 0; + (acc_fir[4] => z[15]) = 0; + (acc_fir[5] => z[15]) = 0; + (acc_fir[0] => z[16]) = 0; + (acc_fir[1] => z[16]) = 0; + (acc_fir[2] => z[16]) = 0; + (acc_fir[3] => z[16]) = 0; + (acc_fir[4] => z[16]) = 0; + (acc_fir[5] => z[16]) = 0; + (acc_fir[0] => z[17]) = 0; + (acc_fir[1] => z[17]) = 0; + (acc_fir[2] => z[17]) = 0; + (acc_fir[3] => z[17]) = 0; + (acc_fir[4] => z[17]) = 0; + (acc_fir[5] => z[17]) = 0; + (acc_fir[0] => z[18]) = 0; + (acc_fir[1] => z[18]) = 0; + (acc_fir[2] => z[18]) = 0; + (acc_fir[3] => z[18]) = 0; + (acc_fir[4] => z[18]) = 0; + (acc_fir[5] => z[18]) = 0; + (acc_fir[0] => z[19]) = 0; + (acc_fir[1] => z[19]) = 0; + (acc_fir[2] => z[19]) = 0; + (acc_fir[3] => z[19]) = 0; + (acc_fir[4] => z[19]) = 0; + (acc_fir[5] => z[19]) = 0; + (acc_fir[0] => z[20]) = 0; + (acc_fir[1] => z[20]) = 0; + (acc_fir[2] => z[20]) = 0; + (acc_fir[3] => z[20]) = 0; + (acc_fir[4] => z[20]) = 0; + (acc_fir[5] => z[20]) = 0; + (acc_fir[0] => z[21]) = 0; + (acc_fir[1] => z[21]) = 0; + (acc_fir[2] => z[21]) = 0; + (acc_fir[3] => z[21]) = 0; + (acc_fir[4] => z[21]) = 0; + (acc_fir[5] => z[21]) = 0; + (acc_fir[0] => z[22]) = 0; + (acc_fir[1] => z[22]) = 0; + (acc_fir[2] => z[22]) = 0; + (acc_fir[3] => z[22]) = 0; + (acc_fir[4] => z[22]) = 0; + (acc_fir[5] => z[22]) = 0; + (acc_fir[0] => z[23]) = 0; + (acc_fir[1] => z[23]) = 0; + (acc_fir[2] => z[23]) = 0; + (acc_fir[3] => z[23]) = 0; + (acc_fir[4] => z[23]) = 0; + (acc_fir[5] => z[23]) = 0; + (acc_fir[0] => z[24]) = 0; + (acc_fir[1] => z[24]) = 0; + (acc_fir[2] => z[24]) = 0; + (acc_fir[3] => z[24]) = 0; + (acc_fir[4] => z[24]) = 0; + (acc_fir[5] => z[24]) = 0; + (acc_fir[0] => z[25]) = 0; + (acc_fir[1] => z[25]) = 0; + (acc_fir[2] => z[25]) = 0; + (acc_fir[3] => z[25]) = 0; + (acc_fir[4] => z[25]) = 0; + (acc_fir[5] => z[25]) = 0; + (acc_fir[0] => z[26]) = 0; + (acc_fir[1] => z[26]) = 0; + (acc_fir[2] => z[26]) = 0; + (acc_fir[3] => z[26]) = 0; + (acc_fir[4] => z[26]) = 0; + (acc_fir[5] => z[26]) = 0; + (acc_fir[0] => z[27]) = 0; + (acc_fir[1] => z[27]) = 0; + (acc_fir[2] => z[27]) = 0; + (acc_fir[3] => z[27]) = 0; + (acc_fir[4] => z[27]) = 0; + (acc_fir[5] => z[27]) = 0; + (acc_fir[0] => z[28]) = 0; + (acc_fir[1] => z[28]) = 0; + (acc_fir[2] => z[28]) = 0; + (acc_fir[3] => z[28]) = 0; + (acc_fir[4] => z[28]) = 0; + (acc_fir[5] => z[28]) = 0; + (acc_fir[0] => z[29]) = 0; + (acc_fir[1] => z[29]) = 0; + (acc_fir[2] => z[29]) = 0; + (acc_fir[3] => z[29]) = 0; + (acc_fir[4] => z[29]) = 0; + (acc_fir[5] => z[29]) = 0; + (acc_fir[0] => z[30]) = 0; + (acc_fir[1] => z[30]) = 0; + (acc_fir[2] => z[30]) = 0; + (acc_fir[3] => z[30]) = 0; + (acc_fir[4] => z[30]) = 0; + (acc_fir[5] => z[30]) = 0; + (acc_fir[0] => z[31]) = 0; + (acc_fir[1] => z[31]) = 0; + (acc_fir[2] => z[31]) = 0; + (acc_fir[3] => z[31]) = 0; + (acc_fir[4] => z[31]) = 0; + (acc_fir[5] => z[31]) = 0; + (acc_fir[0] => z[32]) = 0; + (acc_fir[1] => z[32]) = 0; + (acc_fir[2] => z[32]) = 0; + (acc_fir[3] => z[32]) = 0; + (acc_fir[4] => z[32]) = 0; + (acc_fir[5] => z[32]) = 0; + (acc_fir[0] => z[33]) = 0; + (acc_fir[1] => z[33]) = 0; + (acc_fir[2] => z[33]) = 0; + (acc_fir[3] => z[33]) = 0; + (acc_fir[4] => z[33]) = 0; + (acc_fir[5] => z[33]) = 0; + (acc_fir[0] => z[34]) = 0; + (acc_fir[1] => z[34]) = 0; + (acc_fir[2] => z[34]) = 0; + (acc_fir[3] => z[34]) = 0; + (acc_fir[4] => z[34]) = 0; + (acc_fir[5] => z[34]) = 0; + (acc_fir[0] => z[35]) = 0; + (acc_fir[1] => z[35]) = 0; + (acc_fir[2] => z[35]) = 0; + (acc_fir[3] => z[35]) = 0; + (acc_fir[4] => z[35]) = 0; + (acc_fir[5] => z[35]) = 0; + (acc_fir[0] => z[36]) = 0; + (acc_fir[1] => z[36]) = 0; + (acc_fir[2] => z[36]) = 0; + (acc_fir[3] => z[36]) = 0; + (acc_fir[4] => z[36]) = 0; + (acc_fir[5] => z[36]) = 0; + (acc_fir[0] => z[37]) = 0; + (acc_fir[1] => z[37]) = 0; + (acc_fir[2] => z[37]) = 0; + (acc_fir[3] => z[37]) = 0; + (acc_fir[4] => z[37]) = 0; + (acc_fir[5] => z[37]) = 0; + endspecify +`endif + +endmodule + +module QL_DSP2_MULTADD_REGIN ( + input wire [19:0] a, + input wire [17:0] b, + output wire [37:0] z, + + (* clkbuf_sink *) + input wire clk, + input wire reset, + + input wire [ 2:0] feedback, + input wire [ 5:0] acc_fir, + input wire load_acc, + input wire unsigned_a, + input wire unsigned_b, + + input wire f_mode, + input wire [ 2:0] output_select, + input wire saturate_enable, + input wire [ 5:0] shift_right, + input wire round, + input wire subtract, + input wire register_inputs +); + + parameter [79:0] MODE_BITS = 80'd0; + + localparam [19:0] COEFF_0 = MODE_BITS[19:0]; + localparam [19:0] COEFF_1 = MODE_BITS[39:20]; + localparam [19:0] COEFF_2 = MODE_BITS[59:40]; + localparam [19:0] COEFF_3 = MODE_BITS[79:60]; + + QL_DSP2 #( + .MODE_BITS({COEFF_3, COEFF_2, COEFF_1, COEFF_0}) + ) dsp ( + .a(a), + .b(b), + .dly_b(), + .z(z), + + .f_mode(f_mode), + + .feedback(feedback), + .acc_fir(acc_fir), + .load_acc(load_acc), + + .unsigned_a(unsigned_a), + .unsigned_b(unsigned_b), + + .clk(clk), + .reset(reset), + + .output_select(output_select), // unregistered output: ACCin (2, 3) + .saturate_enable(saturate_enable), + .shift_right(shift_right), + .round(round), + .subtract(subtract), + .register_inputs(register_inputs) // registered inputs + ); + +`ifdef SDF_SIM + specify + (posedge clk => (z +: a)) = 0; + (posedge clk => (z +: b)) = 0; + $setuphold(posedge clk, a, 0, 0); + $setuphold(posedge clk, b, 0, 0); + $setuphold(posedge clk, feedback, 0, 0); + $setuphold(posedge clk, load_acc, 0, 0); + $setuphold(posedge clk, subtract, 0, 0); + $setuphold(posedge clk, acc_fir, 0, 0); + endspecify +`endif + +endmodule + +module QL_DSP2_MULTADD_REGOUT ( + input wire [19:0] a, + input wire [17:0] b, + output wire [37:0] z, + + (* clkbuf_sink *) + input wire clk, + input wire reset, + + input wire [ 2:0] feedback, + input wire [ 5:0] acc_fir, + input wire load_acc, + input wire unsigned_a, + input wire unsigned_b, + + input wire f_mode, + input wire [ 2:0] output_select, + input wire saturate_enable, + input wire [ 5:0] shift_right, + input wire round, + input wire subtract, + input wire register_inputs +); + + parameter [79:0] MODE_BITS = 80'd0; + + localparam [19:0] COEFF_0 = MODE_BITS[19:0]; + localparam [19:0] COEFF_1 = MODE_BITS[39:20]; + localparam [19:0] COEFF_2 = MODE_BITS[59:40]; + localparam [19:0] COEFF_3 = MODE_BITS[79:60]; + + QL_DSP2 #( + .MODE_BITS({COEFF_3, COEFF_2, COEFF_1, COEFF_0}) + ) dsp ( + .a(a), + .b(b), + .dly_b(), + .z(z), + + .f_mode(f_mode), + + .feedback(feedback), + .acc_fir(acc_fir), + .load_acc(load_acc), + + .unsigned_a(unsigned_a), + .unsigned_b(unsigned_b), + + .clk(clk), + .reset(reset), + + .output_select(output_select), // registered output: ACCin (6, 7) + .saturate_enable(saturate_enable), + .shift_right(shift_right), + .round(round), + .subtract(subtract), + .register_inputs(register_inputs) // unregistered inputs + ); + +`ifdef SDF_SIM + specify + (posedge clk => (z +: a)) = 0; + (posedge clk => (z +: b)) = 0; + $setuphold(posedge clk, a, 0, 0); + $setuphold(posedge clk, b, 0, 0); + $setuphold(posedge clk, feedback, 0, 0); + $setuphold(posedge clk, load_acc, 0, 0); + $setuphold(posedge clk, subtract, 0, 0); + $setuphold(posedge clk, acc_fir, 0, 0); + endspecify +`endif + +endmodule + +module QL_DSP2_MULTADD_REGIN_REGOUT ( + input wire [19:0] a, + input wire [17:0] b, + output wire [37:0] z, + + (* clkbuf_sink *) + input wire clk, + input wire reset, + + input wire [ 2:0] feedback, + input wire [ 5:0] acc_fir, + input wire load_acc, + input wire unsigned_a, + input wire unsigned_b, + + input wire f_mode, + input wire [ 2:0] output_select, + input wire saturate_enable, + input wire [ 5:0] shift_right, + input wire round, + input wire subtract, + input wire register_inputs +); + + parameter [79:0] MODE_BITS = 80'd0; + + localparam [19:0] COEFF_0 = MODE_BITS[19:0]; + localparam [19:0] COEFF_1 = MODE_BITS[39:20]; + localparam [19:0] COEFF_2 = MODE_BITS[59:40]; + localparam [19:0] COEFF_3 = MODE_BITS[79:60]; + + QL_DSP2 #( + .MODE_BITS({COEFF_3, COEFF_2, COEFF_1, COEFF_0}) + ) dsp ( + .a(a), + .b(b), + .dly_b(), + .z(z), + + .f_mode(f_mode), + + .feedback(feedback), + .acc_fir(acc_fir), + .load_acc(load_acc), + + .unsigned_a(unsigned_a), + .unsigned_b(unsigned_b), + + .clk(clk), + .reset(reset), + + .output_select(output_select), // registered output: ACCin (6, 7) + .saturate_enable(saturate_enable), + .shift_right(shift_right), + .round(round), + .subtract(subtract), + .register_inputs(register_inputs) // registered inputs + ); + +`ifdef SDF_SIM + specify + (posedge clk => (z +: a)) = 0; + (posedge clk => (z +: b)) = 0; + $setuphold(posedge clk, a, 0, 0); + $setuphold(posedge clk, b, 0, 0); + $setuphold(posedge clk, feedback, 0, 0); + $setuphold(posedge clk, load_acc, 0, 0); + $setuphold(posedge clk, subtract, 0, 0); + $setuphold(posedge clk, acc_fir, 0, 0); + endspecify +`endif + +endmodule + +module QL_DSP2_MULTACC ( + input wire [19:0] a, + input wire [17:0] b, + output wire [37:0] z, + + (* clkbuf_sink *) + input wire clk, + input wire reset, + + input wire load_acc, + input wire [ 2:0] feedback, + input wire unsigned_a, + input wire unsigned_b, + + input wire f_mode, + input wire [ 2:0] output_select, + input wire saturate_enable, + input wire [ 5:0] shift_right, + input wire round, + input wire subtract, + input wire register_inputs +); + + parameter [79:0] MODE_BITS = 80'd0; + + localparam [19:0] COEFF_0 = MODE_BITS[19:0]; + localparam [19:0] COEFF_1 = MODE_BITS[39:20]; + localparam [19:0] COEFF_2 = MODE_BITS[59:40]; + localparam [19:0] COEFF_3 = MODE_BITS[79:60]; + + QL_DSP2 #( + .MODE_BITS({COEFF_3, COEFF_2, COEFF_1, COEFF_0}) + ) dsp ( + .a(a), + .b(b), + .acc_fir(6'b0), + .z(z), + .dly_b(), + + .f_mode(f_mode), + + .feedback(feedback), + .load_acc(load_acc), + + .unsigned_a(unsigned_a), + .unsigned_b(unsigned_b), + + .clk(clk), + .reset(reset), + + .output_select(output_select), // unregistered output: ACCout (1) + .saturate_enable(saturate_enable), + .shift_right(shift_right), + .round(round), + .subtract(subtract), + .register_inputs(register_inputs) // unregistered inputs + ); + +`ifdef SDF_SIM + specify + (posedge clk => (z +: a)) = 0; + (posedge clk => (z +: b)) = 0; + $setuphold(posedge clk, a, 0, 0); + $setuphold(posedge clk, b, 0, 0); + $setuphold(posedge clk, feedback, 0, 0); + $setuphold(posedge clk, load_acc, 0, 0); + $setuphold(posedge clk, subtract, 0, 0); + endspecify +`endif + +endmodule + +module QL_DSP2_MULTACC_REGIN ( + input wire [19:0] a, + input wire [17:0] b, + output wire [37:0] z, + + (* clkbuf_sink *) + input wire clk, + input wire reset, + + input wire [ 2:0] feedback, + input wire load_acc, + input wire unsigned_a, + input wire unsigned_b, + + input wire f_mode, + input wire [ 2:0] output_select, + input wire saturate_enable, + input wire [ 5:0] shift_right, + input wire round, + input wire subtract, + input wire register_inputs +); + + parameter [79:0] MODE_BITS = 80'd0; + + localparam [19:0] COEFF_0 = MODE_BITS[19:0]; + localparam [19:0] COEFF_1 = MODE_BITS[39:20]; + localparam [19:0] COEFF_2 = MODE_BITS[59:40]; + localparam [19:0] COEFF_3 = MODE_BITS[79:60]; + + QL_DSP2 #( + .MODE_BITS({COEFF_3, COEFF_2, COEFF_1, COEFF_0}) + ) dsp ( + .a(a), + .b(b), + .acc_fir(6'b0), + .z(z), + .dly_b(), + + .f_mode(f_mode), + + .feedback(feedback), + .load_acc(load_acc), + + .unsigned_a(unsigned_a), + .unsigned_b(unsigned_b), + + .clk(clk), + .reset(reset), + + .output_select(output_select), // unregistered output: ACCout (1) + .saturate_enable(saturate_enable), + .shift_right(shift_right), + .round(round), + .subtract(subtract), + .register_inputs(register_inputs) // registered inputs + ); + +`ifdef SDF_SIM + specify + (posedge clk => (z +: a)) = 0; + (posedge clk => (z +: b)) = 0; + $setuphold(posedge clk, a, 0, 0); + $setuphold(posedge clk, b, 0, 0); + $setuphold(posedge clk, feedback, 0, 0); + $setuphold(posedge clk, load_acc, 0, 0); + $setuphold(posedge clk, subtract, 0, 0); + endspecify +`endif + +endmodule + +module QL_DSP2_MULTACC_REGOUT ( + input wire [19:0] a, + input wire [17:0] b, + output wire [37:0] z, + + (* clkbuf_sink *) + input wire clk, + input wire reset, + + input wire [ 2:0] feedback, + input wire load_acc, + input wire unsigned_a, + input wire unsigned_b, + + input wire f_mode, + input wire [ 2:0] output_select, + input wire saturate_enable, + input wire [ 5:0] shift_right, + input wire round, + input wire subtract, + input wire register_inputs +); + + parameter [79:0] MODE_BITS = 80'd0; + + localparam [19:0] COEFF_0 = MODE_BITS[19:0]; + localparam [19:0] COEFF_1 = MODE_BITS[39:20]; + localparam [19:0] COEFF_2 = MODE_BITS[59:40]; + localparam [19:0] COEFF_3 = MODE_BITS[79:60]; + + QL_DSP2 #( + .MODE_BITS({COEFF_3, COEFF_2, COEFF_1, COEFF_0}) + ) dsp ( + .a(a), + .b(b), + .acc_fir(6'b0), + .z(z), + .dly_b(), + + .f_mode(f_mode), + + .feedback(feedback), + .load_acc(load_acc), + + .unsigned_a(unsigned_a), + .unsigned_b(unsigned_b), + + .clk(clk), + .reset(reset), + + .output_select(output_select), // registered output: ACCout (5) + .saturate_enable(saturate_enable), + .shift_right(shift_right), + .round(round), + .subtract(subtract), + .register_inputs(register_inputs) // unregistered inputs + ); + +`ifdef SDF_SIM + specify + (posedge clk => (z +: a)) = 0; + (posedge clk => (z +: b)) = 0; + $setuphold(posedge clk, a, 0, 0); + $setuphold(posedge clk, b, 0, 0); + $setuphold(posedge clk, feedback, 0, 0); + $setuphold(posedge clk, load_acc, 0, 0); + $setuphold(posedge clk, subtract, 0, 0); + endspecify +`endif + +endmodule + +module QL_DSP2_MULTACC_REGIN_REGOUT ( + input wire [19:0] a, + input wire [17:0] b, + output wire [37:0] z, + + (* clkbuf_sink *) + input wire clk, + input wire reset, + + input wire [ 2:0] feedback, + input wire load_acc, + input wire unsigned_a, + input wire unsigned_b, + + input wire f_mode, + input wire [ 2:0] output_select, + input wire saturate_enable, + input wire [ 5:0] shift_right, + input wire round, + input wire subtract, + input wire register_inputs +); + + parameter [79:0] MODE_BITS = 80'd0; + + localparam [19:0] COEFF_0 = MODE_BITS[19:0]; + localparam [19:0] COEFF_1 = MODE_BITS[39:20]; + localparam [19:0] COEFF_2 = MODE_BITS[59:40]; + localparam [19:0] COEFF_3 = MODE_BITS[79:60]; + + QL_DSP2 #( + .MODE_BITS({COEFF_3, COEFF_2, COEFF_1, COEFF_0}) + ) dsp ( + .a(a), + .b(b), + .acc_fir(6'b0), + .z(z), + .dly_b(), + + .f_mode(f_mode), + + .feedback(feedback), + .load_acc(load_acc), + + .unsigned_a(unsigned_a), + .unsigned_b(unsigned_b), + + .clk(clk), + .reset(reset), + + .output_select(output_select), // registered output: ACCout (5) + .saturate_enable(saturate_enable), + .shift_right(shift_right), + .round(round), + .subtract(subtract), + .register_inputs(register_inputs) // registered inputs + ); + +`ifdef SDF_SIM + specify + (posedge clk => (z +: a)) = 0; + (posedge clk => (z +: b)) = 0; + $setuphold(posedge clk, a, 0, 0); + $setuphold(posedge clk, b, 0, 0); + $setuphold(posedge clk, feedback, 0, 0); + $setuphold(posedge clk, load_acc, 0, 0); + $setuphold(posedge clk, subtract, 0, 0); + endspecify +`endif + +endmodule + +module dsp_t1_20x18x64_cfg_ports ( + input wire [19:0] a_i, + input wire [17:0] b_i, + input wire [ 5:0] acc_fir_i, + output wire [37:0] z_o, + output wire [17:0] dly_b_o, + + (* clkbuf_sink *) + input wire clock_i, + input wire reset_i, + + input wire [ 2:0] feedback_i, + input wire load_acc_i, + input wire unsigned_a_i, + input wire unsigned_b_i, + + input wire [ 2:0] output_select_i, + input wire saturate_enable_i, + input wire [ 5:0] shift_right_i, + input wire round_i, + input wire subtract_i, + input wire register_inputs_i +); + + parameter [19:0] COEFF_0 = 20'd0; + parameter [19:0] COEFF_1 = 20'd0; + parameter [19:0] COEFF_2 = 20'd0; + parameter [19:0] COEFF_3 = 20'd0; + + QL_DSP2 #( + .MODE_BITS({COEFF_3, COEFF_2, COEFF_1, COEFF_0}) + ) dsp ( + .a(a_i), + .b(b_i), + .z(z_o), + .dly_b(dly_b_o), + + .f_mode(1'b0), // 20x18x64 DSP + + .acc_fir(acc_fir_i), + .feedback(feedback_i), + .load_acc(load_acc_i), + + .unsigned_a(unsigned_a_i), + .unsigned_b(unsigned_b_i), + + .clk(clock_i), + .reset(reset_i), + + .saturate_enable(saturate_enable_i), + .output_select(output_select_i), + .round(round_i), + .shift_right(shift_right_i), + .subtract(subtract_i), + .register_inputs(register_inputs_i) + ); +endmodule + +module dsp_t1_10x9x32_cfg_ports ( + input wire [ 9:0] a_i, + input wire [ 8:0] b_i, + input wire [ 5:0] acc_fir_i, + output wire [18:0] z_o, + output wire [ 8:0] dly_b_o, + + (* clkbuf_sink *) + input wire clock_i, + input wire reset_i, + + input wire [ 2:0] feedback_i, + input wire load_acc_i, + input wire unsigned_a_i, + input wire unsigned_b_i, + + input wire [ 2:0] output_select_i, + input wire saturate_enable_i, + input wire [ 5:0] shift_right_i, + input wire round_i, + input wire subtract_i, + input wire register_inputs_i +); + + parameter [9:0] COEFF_0 = 10'd0; + parameter [9:0] COEFF_1 = 10'd0; + parameter [9:0] COEFF_2 = 10'd0; + parameter [9:0] COEFF_3 = 10'd0; + + wire [18:0] z_rem; + wire [8:0] dly_b_rem; + + QL_DSP2 #( + .MODE_BITS({10'd0, COEFF_3, + 10'd0, COEFF_2, + 10'd0, COEFF_1, + 10'd0, COEFF_0}) + ) dsp ( + .a({10'd0, a_i}), + .b({9'd0, b_i}), + .z({z_rem, z_o}), + .dly_b({dly_b_rem, dly_b_o}), + + .f_mode(1'b1), // 10x9x32 DSP + + .acc_fir(acc_fir_i), + .feedback(feedback_i), + .load_acc(load_acc_i), + + .unsigned_a(unsigned_a_i), + .unsigned_b(unsigned_b_i), + + .clk(clock_i), + .reset(reset_i), + + .saturate_enable(saturate_enable_i), + .output_select(output_select_i), + .round(round_i), + .shift_right(shift_right_i), + .subtract(subtract_i), + .register_inputs(register_inputs_i) + ); +endmodule + +module dsp_t1_sim_cfg_ports # ( + parameter NBITS_ACC = 64, + parameter NBITS_A = 20, + parameter NBITS_B = 18, + parameter NBITS_Z = 38 +)( + input wire [NBITS_A-1:0] a_i, + input wire [NBITS_B-1:0] b_i, + output wire [NBITS_Z-1:0] z_o, + output reg [NBITS_B-1:0] dly_b_o, + + input wire [5:0] acc_fir_i, + input wire [2:0] feedback_i, + input wire load_acc_i, + + input wire unsigned_a_i, + input wire unsigned_b_i, + + input wire clock_i, + input wire s_reset, + + input wire saturate_enable_i, + input wire [2:0] output_select_i, + input wire round_i, + input wire [5:0] shift_right_i, + input wire subtract_i, + input wire register_inputs_i, + input wire [NBITS_A-1:0] coef_0_i, + input wire [NBITS_A-1:0] coef_1_i, + input wire [NBITS_A-1:0] coef_2_i, + input wire [NBITS_A-1:0] coef_3_i +); + +// FIXME: The version of Icarus Verilog from Conda seems not to recognize the +// $error macro. Disable this sanity check for now because of that. + + + // Input registers + reg [NBITS_A-1:0] r_a; + reg [NBITS_B-1:0] r_b; + reg [5:0] r_acc_fir; + reg r_unsigned_a; + reg r_unsigned_b; + reg r_load_acc; + reg [2:0] r_feedback; + reg [5:0] r_shift_d1; + reg [5:0] r_shift_d2; + reg r_subtract; + reg r_sat; + reg r_rnd; + reg [NBITS_ACC-1:0] acc; + + initial begin + r_a <= 0; + r_b <= 0; + + r_acc_fir <= 0; + r_unsigned_a <= 0; + r_unsigned_b <= 0; + r_feedback <= 0; + r_shift_d1 <= 0; + r_shift_d2 <= 0; + r_subtract <= 0; + r_load_acc <= 0; + r_sat <= 0; + r_rnd <= 0; + end + + always @(posedge clock_i or posedge s_reset) begin + if (s_reset) begin + + r_a <= 'h0; + r_b <= 'h0; + + r_acc_fir <= 0; + r_unsigned_a <= 0; + r_unsigned_b <= 0; + r_feedback <= 0; + r_shift_d1 <= 0; + r_shift_d2 <= 0; + r_subtract <= 0; + r_load_acc <= 0; + r_sat <= 0; + r_rnd <= 0; + + end else begin + + r_a <= a_i; + r_b <= b_i; + + r_acc_fir <= acc_fir_i; + r_unsigned_a <= unsigned_a_i; + r_unsigned_b <= unsigned_b_i; + r_feedback <= feedback_i; + r_shift_d1 <= shift_right_i; + r_shift_d2 <= r_shift_d1; + r_subtract <= subtract_i; + r_load_acc <= load_acc_i; + r_sat <= r_sat; + r_rnd <= r_rnd; + + end + end + + // Registered / non-registered input path select + wire [NBITS_A-1:0] a = register_inputs_i ? r_a : a_i; + wire [NBITS_B-1:0] b = register_inputs_i ? r_b : b_i; + + wire [5:0] acc_fir = register_inputs_i ? r_acc_fir : acc_fir_i; + wire unsigned_a = register_inputs_i ? r_unsigned_a : unsigned_a_i; + wire unsigned_b = register_inputs_i ? r_unsigned_b : unsigned_b_i; + wire [2:0] feedback = register_inputs_i ? r_feedback : feedback_i; + wire load_acc = register_inputs_i ? r_load_acc : load_acc_i; + wire subtract = register_inputs_i ? r_subtract : subtract_i; + wire sat = register_inputs_i ? r_sat : saturate_enable_i; + wire rnd = register_inputs_i ? r_rnd : round_i; + + // Shift right control + wire [5:0] shift_d1 = register_inputs_i ? r_shift_d1 : shift_right_i; + wire [5:0] shift_d2 = output_select_i[1] ? shift_d1 : r_shift_d2; + + // Multiplier + wire unsigned_mode = unsigned_a & unsigned_b; + wire [NBITS_A-1:0] mult_a; + assign mult_a = (feedback == 3'h0) ? a : + (feedback == 3'h1) ? a : + (feedback == 3'h2) ? a : + (feedback == 3'h3) ? acc[NBITS_A-1:0] : + (feedback == 3'h4) ? coef_0_i : + (feedback == 3'h5) ? coef_1_i : + (feedback == 3'h6) ? coef_2_i : + coef_3_i; // if feedback == 3'h7 + + wire [NBITS_B-1:0] mult_b = (feedback == 2'h2) ? {NBITS_B{1'b0}} : b; + + wire [NBITS_A-1:0] mult_sgn_a = mult_a[NBITS_A-1]; + wire [NBITS_A-1:0] mult_mag_a = (mult_sgn_a && !unsigned_a) ? (~mult_a + 1) : mult_a; + wire [NBITS_B-1:0] mult_sgn_b = mult_b[NBITS_B-1]; + wire [NBITS_B-1:0] mult_mag_b = (mult_sgn_b && !unsigned_b) ? (~mult_b + 1) : mult_b; + + wire [NBITS_A+NBITS_B-1:0] mult_mag = mult_mag_a * mult_mag_b; + wire mult_sgn = (mult_sgn_a && !unsigned_a) ^ (mult_sgn_b && !unsigned_b); + + wire [NBITS_A+NBITS_B-1:0] mult = (unsigned_a && unsigned_b) ? + (mult_a * mult_b) : (mult_sgn ? (~mult_mag + 1) : mult_mag); + + // Sign extension + wire [NBITS_ACC-1:0] mult_xtnd = unsigned_mode ? + {{(NBITS_ACC-NBITS_A-NBITS_B){1'b0}}, mult[NBITS_A+NBITS_B-1:0]} : + {{(NBITS_ACC-NBITS_A-NBITS_B){mult[NBITS_A+NBITS_B-1]}}, mult[NBITS_A+NBITS_B-1:0]}; + + // Adder + wire [NBITS_ACC-1:0] acc_fir_int = unsigned_a ? {{(NBITS_ACC-NBITS_A){1'b0}}, a} : + {{(NBITS_ACC-NBITS_A){a[NBITS_A-1]}}, a} ; + + wire [NBITS_ACC-1:0] add_a = (subtract) ? (~mult_xtnd + 1) : mult_xtnd; + wire [NBITS_ACC-1:0] add_b = (feedback_i == 3'h0) ? acc : + (feedback_i == 3'h1) ? {{NBITS_ACC}{1'b0}} : (acc_fir_int << acc_fir); + + wire [NBITS_ACC-1:0] add_o = add_a + add_b; + + // Accumulator + initial acc <= 0; + + always @(posedge clock_i or posedge s_reset) + if (s_reset) acc <= 'h0; + else begin + if (load_acc) + acc <= add_o; + else + acc <= acc; + end + + // Adder/accumulator output selection + wire [NBITS_ACC-1:0] acc_out = (output_select_i[1]) ? add_o : acc; + + // Round, shift, saturate + wire [NBITS_ACC-1:0] acc_rnd = (rnd && (shift_right_i != 0)) ? (acc_out + ({{(NBITS_ACC-1){1'b0}}, 1'b1} << (shift_right_i - 1))) : + acc_out; + + wire [NBITS_ACC-1:0] acc_shr = (unsigned_mode) ? (acc_rnd >> shift_right_i) : + (acc_rnd >>> shift_right_i); + + wire [NBITS_ACC-1:0] acc_sat_u = (acc_shr[NBITS_ACC-1:NBITS_Z] != 0) ? {{(NBITS_ACC-NBITS_Z){1'b0}},{NBITS_Z{1'b1}}} : + {{(NBITS_ACC-NBITS_Z){1'b0}},{acc_shr[NBITS_Z-1:0]}}; + + wire [NBITS_ACC-1:0] acc_sat_s = ((|acc_shr[NBITS_ACC-1:NBITS_Z-1] == 1'b0) || + (&acc_shr[NBITS_ACC-1:NBITS_Z-1] == 1'b1)) ? {{(NBITS_ACC-NBITS_Z){1'b0}},{acc_shr[NBITS_Z-1:0]}} : + {{(NBITS_ACC-NBITS_Z){1'b0}},{acc_shr[NBITS_ACC-1],{NBITS_Z-1{~acc_shr[NBITS_ACC-1]}}}}; + + wire [NBITS_ACC-1:0] acc_sat = (sat) ? ((unsigned_mode) ? acc_sat_u : acc_sat_s) : acc_shr; + + // Output signals + wire [NBITS_Z-1:0] z0; + reg [NBITS_Z-1:0] z1; + wire [NBITS_Z-1:0] z2; + + assign z0 = mult_xtnd[NBITS_Z-1:0]; + assign z2 = acc_sat[NBITS_Z-1:0]; + + initial z1 <= 0; + + always @(posedge clock_i or posedge s_reset) + if (s_reset) + z1 <= 0; + else begin + z1 <= (output_select_i == 3'b100) ? z0 : z2; + end + + // Output mux + assign z_o = (output_select_i == 3'h0) ? z0 : + (output_select_i == 3'h1) ? z2 : + (output_select_i == 3'h2) ? z2 : + (output_select_i == 3'h3) ? z2 : + (output_select_i == 3'h4) ? z1 : + (output_select_i == 3'h5) ? z1 : + (output_select_i == 3'h6) ? z1 : + z1; // if output_select_i == 3'h7 + + // B input delayed passthrough + initial dly_b_o <= 0; + + always @(posedge clock_i or posedge s_reset) + if (s_reset) + dly_b_o <= 0; + else + dly_b_o <= b_i; + +endmodule + + + +// ---------------------------------------- // +// ----- DSP cells simulation modules ----- // +// ------ Control bits in parameters ------ // +// ---------------------------------------- // + +module QL_DSP3 ( // TODO: Name subject to change + input wire [19:0] a, + input wire [17:0] b, + input wire [ 5:0] acc_fir, + output wire [37:0] z, + output wire [17:0] dly_b, + + (* clkbuf_sink *) + input wire clk, + input wire reset, + + input wire [2:0] feedback, + input wire load_acc, + input wire unsigned_a, + input wire unsigned_b, + input wire subtract +); + + parameter [92:0] MODE_BITS = 93'b0; + + localparam [19:0] COEFF_0 = MODE_BITS[19:0]; + localparam [19:0] COEFF_1 = MODE_BITS[39:20]; + localparam [19:0] COEFF_2 = MODE_BITS[59:40]; + localparam [19:0] COEFF_3 = MODE_BITS[79:60]; + + localparam [0:0] F_MODE = MODE_BITS[80]; + localparam [2:0] OUTPUT_SELECT = MODE_BITS[83:81]; + localparam [0:0] SATURATE_ENABLE = MODE_BITS[84]; + localparam [5:0] SHIFT_RIGHT = MODE_BITS[90:85]; + localparam [0:0] ROUND = MODE_BITS[91]; + localparam [0:0] REGISTER_INPUTS = MODE_BITS[92]; + + localparam NBITS_ACC = 64; + localparam NBITS_A = 20; + localparam NBITS_B = 18; + localparam NBITS_Z = 38; + + // Fractured + generate if(F_MODE == 1'b1) begin + + wire [(NBITS_Z/2)-1:0] dsp_frac0_z; + wire [(NBITS_Z/2)-1:0] dsp_frac1_z; + + wire [(NBITS_B/2)-1:0] dsp_frac0_dly_b; + wire [(NBITS_B/2)-1:0] dsp_frac1_dly_b; + + dsp_t1_sim_cfg_params #( + .NBITS_A (NBITS_A/2), + .NBITS_B (NBITS_B/2), + .NBITS_ACC (NBITS_ACC/2), + .NBITS_Z (NBITS_Z/2), + .OUTPUT_SELECT (OUTPUT_SELECT), + .SATURATE_ENABLE (SATURATE_ENABLE), + .SHIFT_RIGHT (SHIFT_RIGHT), + .ROUND (ROUND), + .REGISTER_INPUTS (REGISTER_INPUTS) + ) dsp_frac0 ( + .a_i(a[(NBITS_A/2)-1:0]), + .b_i(b[(NBITS_B/2)-1:0]), + .z_o(dsp_frac0_z), + .dly_b_o(dsp_frac0_dly_b), + + .acc_fir_i(acc_fir), + .feedback_i(feedback), + .load_acc_i(load_acc), + + .unsigned_a_i(unsigned_a), + .unsigned_b_i(unsigned_b), + + .clock_i(clk), + .s_reset(reset), + + .subtract_i(subtract), + .coef_0_i(COEFF_0[(NBITS_A/2)-1:0]), + .coef_1_i(COEFF_1[(NBITS_A/2)-1:0]), + .coef_2_i(COEFF_2[(NBITS_A/2)-1:0]), + .coef_3_i(COEFF_3[(NBITS_A/2)-1:0]) + ); + + dsp_t1_sim_cfg_params #( + .NBITS_A (NBITS_A/2), + .NBITS_B (NBITS_B/2), + .NBITS_ACC (NBITS_ACC/2), + .NBITS_Z (NBITS_Z/2), + .OUTPUT_SELECT (OUTPUT_SELECT), + .SATURATE_ENABLE (SATURATE_ENABLE), + .SHIFT_RIGHT (SHIFT_RIGHT), + .ROUND (ROUND), + .REGISTER_INPUTS (REGISTER_INPUTS) + ) dsp_frac1 ( + .a_i(a[NBITS_A-1:NBITS_A/2]), + .b_i(b[NBITS_B-1:NBITS_B/2]), + .z_o(dsp_frac1_z), + .dly_b_o(dsp_frac1_dly_b), + .acc_fir_i(acc_fir), + .feedback_i(feedback), + .load_acc_i(load_acc), + + .unsigned_a_i(unsigned_a), + .unsigned_b_i(unsigned_b), + + .clock_i(clk), + .s_reset(reset), + + .subtract_i(subtract), + .coef_0_i(COEFF_0[NBITS_A-1:NBITS_A/2]), + .coef_1_i(COEFF_1[NBITS_A-1:NBITS_A/2]), + .coef_2_i(COEFF_2[NBITS_A-1:NBITS_A/2]), + .coef_3_i(COEFF_3[NBITS_A-1:NBITS_A/2]) + ); + + assign z = {dsp_frac1_z, dsp_frac0_z}; + assign dly_b = {dsp_frac1_dly_b, dsp_frac0_dly_b}; + + // Whole + end else begin + + dsp_t1_sim_cfg_params #( + .NBITS_A (NBITS_A), + .NBITS_B (NBITS_B), + .NBITS_ACC (NBITS_ACC), + .NBITS_Z (NBITS_Z), + .OUTPUT_SELECT (OUTPUT_SELECT), + .SATURATE_ENABLE (SATURATE_ENABLE), + .SHIFT_RIGHT (SHIFT_RIGHT), + .ROUND (ROUND), + .REGISTER_INPUTS (REGISTER_INPUTS) + ) dsp_full ( + .a_i(a), + .b_i(b), + .z_o(z), + .dly_b_o(dly_b), + + .acc_fir_i(acc_fir), + .feedback_i(feedback), + .load_acc_i(load_acc), + + .unsigned_a_i(unsigned_a), + .unsigned_b_i(unsigned_b), + + .clock_i(clk), + .s_reset(reset), + + .subtract_i(subtract), + .coef_0_i(COEFF_0), + .coef_1_i(COEFF_1), + .coef_2_i(COEFF_2), + .coef_3_i(COEFF_3) + ); + + end endgenerate + +endmodule + +module QL_DSP3_MULT ( // TODO: Name subject to change + input wire [19:0] a, + input wire [17:0] b, + output wire [37:0] z, + + input wire reset, + + input wire [2:0] feedback, + input wire unsigned_a, + input wire unsigned_b +); + + parameter [92:0] MODE_BITS = 93'b0; + + localparam [19:0] COEFF_0 = MODE_BITS[19:0]; + localparam [19:0] COEFF_1 = MODE_BITS[39:20]; + localparam [19:0] COEFF_2 = MODE_BITS[59:40]; + localparam [19:0] COEFF_3 = MODE_BITS[79:60]; + + localparam [0:0] F_MODE = MODE_BITS[80]; + localparam [2:0] OUTPUT_SELECT = MODE_BITS[83:81]; // unregistered output: a * b (0) + localparam [0:0] SATURATE_ENABLE = MODE_BITS[84]; + localparam [5:0] SHIFT_RIGHT = MODE_BITS[90:85]; + localparam [0:0] ROUND = MODE_BITS[91]; + localparam [0:0] REGISTER_INPUTS = MODE_BITS[92]; // unregistered inputs + + QL_DSP3 #( + .MODE_BITS({ + REGISTER_INPUTS, + ROUND, + SHIFT_RIGHT, + SATURATE_ENABLE, + OUTPUT_SELECT, + F_MODE, + COEFF_3, + COEFF_2, + COEFF_1, + COEFF_0 + }) + ) dsp ( + .a(a), + .b(b), + .z(z), + + .reset(reset), + + .feedback(feedback), + + .unsigned_a(unsigned_a), + .unsigned_b(unsigned_b) + ); +endmodule + +module QL_DSP3_MULT_REGIN ( // TODO: Name subject to change + input wire [19:0] a, + input wire [17:0] b, + output wire [37:0] z, + + (* clkbuf_sink *) + input wire clk, + input wire reset, + + input wire [2:0] feedback, + + input wire unsigned_a, + input wire unsigned_b +); + + wire [37:0] dly_b_o; + parameter [92:0] MODE_BITS = 93'b0; + + localparam [19:0] COEFF_0 = MODE_BITS[19:0]; + localparam [19:0] COEFF_1 = MODE_BITS[39:20]; + localparam [19:0] COEFF_2 = MODE_BITS[59:40]; + localparam [19:0] COEFF_3 = MODE_BITS[79:60]; + + localparam [0:0] F_MODE = MODE_BITS[80]; + localparam [2:0] OUTPUT_SELECT = MODE_BITS[83:81]; // unregistered output: a * b (0) + localparam [0:0] SATURATE_ENABLE = MODE_BITS[84]; + localparam [5:0] SHIFT_RIGHT = MODE_BITS[90:85]; + localparam [0:0] ROUND = MODE_BITS[91]; + localparam [0:0] REGISTER_INPUTS = MODE_BITS[92]; // registered inputs + + QL_DSP3 #( + .MODE_BITS({ + REGISTER_INPUTS, + ROUND, + SHIFT_RIGHT, + SATURATE_ENABLE, + OUTPUT_SELECT, + F_MODE, + COEFF_3, + COEFF_2, + COEFF_1, + COEFF_0 + }) + ) dsp ( + .a(a), + .b(b), + .z(z), + + .feedback(feedback), + + .unsigned_a(unsigned_a), + .unsigned_b(unsigned_b), + + .clk(clk), + .reset(reset) + ); +endmodule + +module QL_DSP3_MULT_REGOUT ( // TODO: Name subject to change + input wire [19:0] a, + input wire [17:0] b, + output wire [37:0] z, + + (* clkbuf_sink *) + input wire clk, + input wire reset, + + input wire [2:0] feedback, + + input wire unsigned_a, + input wire unsigned_b +); + + parameter [92:0] MODE_BITS = 93'b0; + + localparam [19:0] COEFF_0 = MODE_BITS[19:0]; + localparam [19:0] COEFF_1 = MODE_BITS[39:20]; + localparam [19:0] COEFF_2 = MODE_BITS[59:40]; + localparam [19:0] COEFF_3 = MODE_BITS[79:60]; + + localparam [0:0] F_MODE = MODE_BITS[80]; + localparam [2:0] OUTPUT_SELECT = MODE_BITS[83:81]; // registered output: a * b (4) + localparam [0:0] SATURATE_ENABLE = MODE_BITS[84]; + localparam [5:0] SHIFT_RIGHT = MODE_BITS[90:85]; + localparam [0:0] ROUND = MODE_BITS[91]; + localparam [0:0] REGISTER_INPUTS = MODE_BITS[92]; // unregistered inputs + + QL_DSP3 #( + .MODE_BITS({ + REGISTER_INPUTS, + ROUND, + SHIFT_RIGHT, + SATURATE_ENABLE, + OUTPUT_SELECT, + F_MODE, + COEFF_3, + COEFF_2, + COEFF_1, + COEFF_0 + }) + ) dsp ( + .a(a), + .b(b), + .z(z), + + .feedback(feedback), + + .unsigned_a(unsigned_a), + .unsigned_b(unsigned_b), + + .clk(clk), + .reset(reset) + ); +endmodule + +module QL_DSP3_MULT_REGIN_REGOUT ( // TODO: Name subject to change + input wire [19:0] a, + input wire [17:0] b, + output wire [37:0] z, + + (* clkbuf_sink *) + input wire clk, + input wire reset, + + input wire [2:0] feedback, + + input wire unsigned_a, + input wire unsigned_b +); + + parameter [92:0] MODE_BITS = 93'b0; + + localparam [19:0] COEFF_0 = MODE_BITS[19:0]; + localparam [19:0] COEFF_1 = MODE_BITS[39:20]; + localparam [19:0] COEFF_2 = MODE_BITS[59:40]; + localparam [19:0] COEFF_3 = MODE_BITS[79:60]; + + localparam [0:0] F_MODE = MODE_BITS[80]; + localparam [2:0] OUTPUT_SELECT = MODE_BITS[83:81]; // registered output: a * b (4) + localparam [0:0] SATURATE_ENABLE = MODE_BITS[84]; + localparam [5:0] SHIFT_RIGHT = MODE_BITS[90:85]; + localparam [0:0] ROUND = MODE_BITS[91]; + localparam [0:0] REGISTER_INPUTS = MODE_BITS[92]; // unregistered inputs + + QL_DSP3 #( + .MODE_BITS({ + REGISTER_INPUTS, + ROUND, + SHIFT_RIGHT, + SATURATE_ENABLE, + OUTPUT_SELECT, + F_MODE, + COEFF_3, + COEFF_2, + COEFF_1, + COEFF_0 + }) + ) dsp ( + .a(a), + .b(b), + .z(z), + + .feedback(feedback), + + .unsigned_a(unsigned_a), + .unsigned_b(unsigned_b), + + .clk(clk), + .reset(reset) + ); +endmodule + +module QL_DSP3_MULTADD ( + input wire [19:0] a, + input wire [17:0] b, + output wire [37:0] z, + + input wire reset, + + input wire [ 2:0] feedback, + input wire [ 5:0] acc_fir, + input wire load_acc, + input wire unsigned_a, + input wire unsigned_b, + input wire subtract +); + + parameter [92:0] MODE_BITS = 93'b0; + + localparam [19:0] COEFF_0 = MODE_BITS[19:0]; + localparam [19:0] COEFF_1 = MODE_BITS[39:20]; + localparam [19:0] COEFF_2 = MODE_BITS[59:40]; + localparam [19:0] COEFF_3 = MODE_BITS[79:60]; + + localparam [0:0] F_MODE = MODE_BITS[80]; + localparam [2:0] OUTPUT_SELECT = MODE_BITS[83:81]; + localparam [0:0] SATURATE_ENABLE = MODE_BITS[84]; + localparam [5:0] SHIFT_RIGHT = MODE_BITS[90:85]; + localparam [0:0] ROUND = MODE_BITS[91]; + localparam [0:0] REGISTER_INPUTS = MODE_BITS[92]; + + QL_DSP3 #( + .MODE_BITS({ + REGISTER_INPUTS, + ROUND, + SHIFT_RIGHT, + SATURATE_ENABLE, + OUTPUT_SELECT, + F_MODE, + COEFF_3, + COEFF_2, + COEFF_1, + COEFF_0 + }) + ) dsp ( + .a(a), + .b(b), + .z(z), + + .feedback(feedback), + .acc_fir(acc_fir), + .load_acc(load_acc), + + .unsigned_a(unsigned_a), + .unsigned_b(unsigned_b), + + .reset(reset), + .subtract(subtract) + ); +endmodule + +module QL_DSP3_MULTADD_REGIN ( + input wire [19:0] a, + input wire [17:0] b, + output wire [37:0] z, + + (* clkbuf_sink *) + input wire clk, + input wire reset, + + input wire [ 2:0] feedback, + input wire [ 5:0] acc_fir, + input wire load_acc, + input wire unsigned_a, + input wire unsigned_b, + input wire subtract +); + + parameter [92:0] MODE_BITS = 93'b0; + + localparam [19:0] COEFF_0 = MODE_BITS[19:0]; + localparam [19:0] COEFF_1 = MODE_BITS[39:20]; + localparam [19:0] COEFF_2 = MODE_BITS[59:40]; + localparam [19:0] COEFF_3 = MODE_BITS[79:60]; + + localparam [0:0] F_MODE = MODE_BITS[80]; + localparam [2:0] OUTPUT_SELECT = MODE_BITS[83:81]; + localparam [0:0] SATURATE_ENABLE = MODE_BITS[84]; + localparam [5:0] SHIFT_RIGHT = MODE_BITS[90:85]; + localparam [0:0] ROUND = MODE_BITS[91]; + localparam [0:0] REGISTER_INPUTS = MODE_BITS[92]; + + QL_DSP3 #( + .MODE_BITS({ + REGISTER_INPUTS, + ROUND, + SHIFT_RIGHT, + SATURATE_ENABLE, + OUTPUT_SELECT, + F_MODE, + COEFF_3, + COEFF_2, + COEFF_1, + COEFF_0 + }) + ) dsp ( + .a(a), + .b(b), + .z(z), + + .feedback(feedback), + .acc_fir(acc_fir), + .load_acc(load_acc), + + .unsigned_a(unsigned_a), + .unsigned_b(unsigned_b), + + .clk(clk), + .reset(reset), + .subtract(subtract) + ); +endmodule + +module QL_DSP3_MULTADD_REGOUT ( + input wire [19:0] a, + input wire [17:0] b, + output wire [37:0] z, + + (* clkbuf_sink *) + input wire clk, + input wire reset, + + input wire [ 2:0] feedback, + input wire [ 5:0] acc_fir, + input wire load_acc, + input wire unsigned_a, + input wire unsigned_b, + input wire subtract +); + + parameter [92:0] MODE_BITS = 93'b0; + + localparam [19:0] COEFF_0 = MODE_BITS[19:0]; + localparam [19:0] COEFF_1 = MODE_BITS[39:20]; + localparam [19:0] COEFF_2 = MODE_BITS[59:40]; + localparam [19:0] COEFF_3 = MODE_BITS[79:60]; + + localparam [0:0] F_MODE = MODE_BITS[80]; + localparam [2:0] OUTPUT_SELECT = MODE_BITS[83:81]; + localparam [0:0] SATURATE_ENABLE = MODE_BITS[84]; + localparam [5:0] SHIFT_RIGHT = MODE_BITS[90:85]; + localparam [0:0] ROUND = MODE_BITS[91]; + localparam [0:0] REGISTER_INPUTS = MODE_BITS[92]; + + QL_DSP3 #( + .MODE_BITS({ + REGISTER_INPUTS, + ROUND, + SHIFT_RIGHT, + SATURATE_ENABLE, + OUTPUT_SELECT, + F_MODE, + COEFF_3, + COEFF_2, + COEFF_1, + COEFF_0 + }) + ) dsp ( + .a(a), + .b(b), + .z(z), + + .feedback(feedback), + .acc_fir(acc_fir), + .load_acc(load_acc), + + .unsigned_a(unsigned_a), + .unsigned_b(unsigned_b), + + .clk(clk), + .reset(reset), + .subtract(subtract) + ); +endmodule + +module QL_DSP3_MULTADD_REGIN_REGOUT ( + input wire [19:0] a, + input wire [17:0] b, + output wire [37:0] z, + + (* clkbuf_sink *) + input wire clk, + input wire reset, + + input wire [ 2:0] feedback, + input wire [ 5:0] acc_fir, + input wire load_acc, + input wire unsigned_a, + input wire unsigned_b, + input wire subtract +); + + parameter [92:0] MODE_BITS = 93'b0; + + localparam [19:0] COEFF_0 = MODE_BITS[19:0]; + localparam [19:0] COEFF_1 = MODE_BITS[39:20]; + localparam [19:0] COEFF_2 = MODE_BITS[59:40]; + localparam [19:0] COEFF_3 = MODE_BITS[79:60]; + + localparam [0:0] F_MODE = MODE_BITS[80]; + localparam [2:0] OUTPUT_SELECT = MODE_BITS[83:81]; + localparam [0:0] SATURATE_ENABLE = MODE_BITS[84]; + localparam [5:0] SHIFT_RIGHT = MODE_BITS[90:85]; + localparam [0:0] ROUND = MODE_BITS[91]; + localparam [0:0] REGISTER_INPUTS = MODE_BITS[92]; + + QL_DSP3 #( + .MODE_BITS({ + REGISTER_INPUTS, + ROUND, + SHIFT_RIGHT, + SATURATE_ENABLE, + OUTPUT_SELECT, + F_MODE, + COEFF_3, + COEFF_2, + COEFF_1, + COEFF_0 + }) + ) dsp ( + .a(a), + .b(b), + .z(z), + + .feedback(feedback), + .acc_fir(acc_fir), + .load_acc(load_acc), + + .unsigned_a(unsigned_a), + .unsigned_b(unsigned_b), + + .clk(clk), + .reset(reset), + .subtract(subtract) + ); +endmodule + +module QL_DSP3_MULTACC ( + input wire [19:0] a, + input wire [17:0] b, + output wire [37:0] z, + + (* clkbuf_sink *) + input wire clk, + input wire reset, + + input wire [ 2:0] feedback, + input wire load_acc, + input wire unsigned_a, + input wire unsigned_b, + input wire subtract +); + + parameter [92:0] MODE_BITS = 93'b0; + + localparam [19:0] COEFF_0 = MODE_BITS[19:0]; + localparam [19:0] COEFF_1 = MODE_BITS[39:20]; + localparam [19:0] COEFF_2 = MODE_BITS[59:40]; + localparam [19:0] COEFF_3 = MODE_BITS[79:60]; + + localparam [0:0] F_MODE = MODE_BITS[80]; + localparam [2:0] OUTPUT_SELECT = MODE_BITS[83:81]; + localparam [0:0] SATURATE_ENABLE = MODE_BITS[84]; + localparam [5:0] SHIFT_RIGHT = MODE_BITS[90:85]; + localparam [0:0] ROUND = MODE_BITS[91]; + localparam [0:0] REGISTER_INPUTS = MODE_BITS[92]; + + QL_DSP3 #( + .MODE_BITS({ + REGISTER_INPUTS, + ROUND, + SHIFT_RIGHT, + SATURATE_ENABLE, + OUTPUT_SELECT, + F_MODE, + COEFF_3, + COEFF_2, + COEFF_1, + COEFF_0 + }) + ) dsp ( + .a(a), + .b(b), + .z(z), + + .feedback(feedback), + .load_acc(load_acc), + + .unsigned_a(unsigned_a), + .unsigned_b(unsigned_b), + + .clk(clk), + .reset(reset), + .subtract(subtract) + ); +endmodule + +module QL_DSP3_MULTACC_REGIN ( + input wire [19:0] a, + input wire [17:0] b, + output wire [37:0] z, + + (* clkbuf_sink *) + input wire clk, + input wire reset, + + input wire [ 2:0] feedback, + input wire load_acc, + input wire unsigned_a, + input wire unsigned_b, + input wire subtract +); + + parameter [92:0] MODE_BITS = 93'b0; + + localparam [19:0] COEFF_0 = MODE_BITS[19:0]; + localparam [19:0] COEFF_1 = MODE_BITS[39:20]; + localparam [19:0] COEFF_2 = MODE_BITS[59:40]; + localparam [19:0] COEFF_3 = MODE_BITS[79:60]; + + localparam [0:0] F_MODE = MODE_BITS[80]; + localparam [2:0] OUTPUT_SELECT = MODE_BITS[83:81]; + localparam [0:0] SATURATE_ENABLE = MODE_BITS[84]; + localparam [5:0] SHIFT_RIGHT = MODE_BITS[90:85]; + localparam [0:0] ROUND = MODE_BITS[91]; + localparam [0:0] REGISTER_INPUTS = MODE_BITS[92]; + + QL_DSP3 #( + .MODE_BITS({ + REGISTER_INPUTS, + ROUND, + SHIFT_RIGHT, + SATURATE_ENABLE, + OUTPUT_SELECT, + F_MODE, + COEFF_3, + COEFF_2, + COEFF_1, + COEFF_0 + }) + ) dsp ( + .a(a), + .b(b), + .z(z), + + .feedback(feedback), + .load_acc(load_acc), + + .unsigned_a(unsigned_a), + .unsigned_b(unsigned_b), + + .clk(clk), + .reset(reset), + .subtract(subtract) + ); +endmodule + +module QL_DSP3_MULTACC_REGOUT ( + input wire [19:0] a, + input wire [17:0] b, + output wire [37:0] z, + + (* clkbuf_sink *) + input wire clk, + input wire reset, + + input wire [ 2:0] feedback, + input wire load_acc, + input wire unsigned_a, + input wire unsigned_b, + input wire subtract +); + + parameter [92:0] MODE_BITS = 93'b0; + + localparam [19:0] COEFF_0 = MODE_BITS[19:0]; + localparam [19:0] COEFF_1 = MODE_BITS[39:20]; + localparam [19:0] COEFF_2 = MODE_BITS[59:40]; + localparam [19:0] COEFF_3 = MODE_BITS[79:60]; + + localparam [0:0] F_MODE = MODE_BITS[80]; + localparam [2:0] OUTPUT_SELECT = MODE_BITS[83:81]; + localparam [0:0] SATURATE_ENABLE = MODE_BITS[84]; + localparam [5:0] SHIFT_RIGHT = MODE_BITS[90:85]; + localparam [0:0] ROUND = MODE_BITS[91]; + localparam [0:0] REGISTER_INPUTS = MODE_BITS[92]; + + QL_DSP3 #( + .MODE_BITS({ + REGISTER_INPUTS, + ROUND, + SHIFT_RIGHT, + SATURATE_ENABLE, + OUTPUT_SELECT, + F_MODE, + COEFF_3, + COEFF_2, + COEFF_1, + COEFF_0 + }) + ) dsp ( + .a(a), + .b(b), + .z(z), + + .feedback(feedback), + .load_acc(load_acc), + + .unsigned_a(unsigned_a), + .unsigned_b(unsigned_b), + + .clk(clk), + .reset(reset), + .subtract(subtract) + ); +endmodule + +module QL_DSP3_MULTACC_REGIN_REGOUT ( + input wire [19:0] a, + input wire [17:0] b, + output wire [37:0] z, + + (* clkbuf_sink *) + input wire clk, + input wire reset, + + input wire [ 2:0] feedback, + input wire load_acc, + input wire unsigned_a, + input wire unsigned_b, + input wire subtract +); + + parameter [92:0] MODE_BITS = 93'b0; + + localparam [19:0] COEFF_0 = MODE_BITS[19:0]; + localparam [19:0] COEFF_1 = MODE_BITS[39:20]; + localparam [19:0] COEFF_2 = MODE_BITS[59:40]; + localparam [19:0] COEFF_3 = MODE_BITS[79:60]; + + localparam [0:0] F_MODE = MODE_BITS[80]; + localparam [2:0] OUTPUT_SELECT = MODE_BITS[83:81]; + localparam [0:0] SATURATE_ENABLE = MODE_BITS[84]; + localparam [5:0] SHIFT_RIGHT = MODE_BITS[90:85]; + localparam [0:0] ROUND = MODE_BITS[91]; + localparam [0:0] REGISTER_INPUTS = MODE_BITS[92]; + + QL_DSP3 #( + .MODE_BITS({ + REGISTER_INPUTS, + ROUND, + SHIFT_RIGHT, + SATURATE_ENABLE, + OUTPUT_SELECT, + F_MODE, + COEFF_3, + COEFF_2, + COEFF_1, + COEFF_0 + }) + ) dsp ( + .a(a), + .b(b), + .z(z), + + .feedback(feedback), + .load_acc(load_acc), + + .unsigned_a(unsigned_a), + .unsigned_b(unsigned_b), + + .clk(clk), + .reset(reset), + .subtract(subtract) + ); +endmodule + +module dsp_t1_20x18x64_cfg_params ( + input wire [19:0] a_i, + input wire [17:0] b_i, + input wire [ 5:0] acc_fir_i, + output wire [37:0] z_o, + output wire [17:0] dly_b_o, + + (* clkbuf_sink *) + input wire clock_i, + input wire reset_i, + + input wire [ 2:0] feedback_i, + input wire load_acc_i, + input wire unsigned_a_i, + input wire unsigned_b_i, + input wire subtract_i +); + + parameter [19:0] COEFF_0 = 20'b0; + parameter [19:0] COEFF_1 = 20'b0; + parameter [19:0] COEFF_2 = 20'b0; + parameter [19:0] COEFF_3 = 20'b0; + + parameter [2:0] OUTPUT_SELECT = 3'b0; + parameter [0:0] SATURATE_ENABLE = 1'b0; + parameter [5:0] SHIFT_RIGHT = 6'b0; + parameter [0:0] ROUND = 1'b0; + parameter [0:0] REGISTER_INPUTS = 1'b0; + + QL_DSP3 #( + .MODE_BITS ({ + REGISTER_INPUTS, + ROUND, + SHIFT_RIGHT, + SATURATE_ENABLE, + OUTPUT_SELECT, + 1'b0, // Not fractured + COEFF_3, + COEFF_2, + COEFF_1, + COEFF_0 + }) + ) dsp ( + .a(a_i), + .b(b_i), + .z(z_o), + .dly_b(dly_b_o), + + .acc_fir(acc_fir_i), + .feedback(feedback_i), + .load_acc(load_acc_i), + + .unsigned_a(unsigned_a_i), + .unsigned_b(unsigned_b_i), + + .clk(clock_i), + .reset(reset_i), + .subtract(subtract_i) + ); +endmodule + +module dsp_t1_10x9x32_cfg_params ( + input wire [ 9:0] a_i, + input wire [ 8:0] b_i, + input wire [ 5:0] acc_fir_i, + output wire [18:0] z_o, + output wire [ 8:0] dly_b_o, + + (* clkbuf_sink *) + input wire clock_i, + input wire reset_i, + + input wire [ 2:0] feedback_i, + input wire load_acc_i, + input wire unsigned_a_i, + input wire unsigned_b_i, + input wire subtract_i +); + + parameter [9:0] COEFF_0 = 10'b0; + parameter [9:0] COEFF_1 = 10'b0; + parameter [9:0] COEFF_2 = 10'b0; + parameter [9:0] COEFF_3 = 10'b0; + + parameter [2:0] OUTPUT_SELECT = 3'b0; + parameter [0:0] SATURATE_ENABLE = 1'b0; + parameter [5:0] SHIFT_RIGHT = 6'b0; + parameter [0:0] ROUND = 1'b0; + parameter [0:0] REGISTER_INPUTS = 1'b0; + + wire [18:0] z_rem; + wire [8:0] dly_b_rem; + + QL_DSP3 #( + .MODE_BITS ({ + REGISTER_INPUTS, + ROUND, + SHIFT_RIGHT, + SATURATE_ENABLE, + OUTPUT_SELECT, + 1'b1, // Fractured + 10'd0, COEFF_3, + 10'd0, COEFF_2, + 10'd0, COEFF_1, + 10'd0, COEFF_0 + }) + ) dsp ( + .a({10'b0, a_i}), + .b({9'b0, b_i}), + .z({z_rem, z_o}), + .dly_b({dly_b_rem, dly_b_o}), + + .acc_fir(acc_fir_i), + .feedback(feedback_i), + .load_acc(load_acc_i), + + .unsigned_a(unsigned_a_i), + .unsigned_b(unsigned_b_i), + + .clk(clock_i), + .reset(reset_i), + .subtract(subtract_i) + ); +endmodule + +module dsp_t1_sim_cfg_params # ( + parameter NBITS_ACC = 64, + parameter NBITS_A = 20, + parameter NBITS_B = 18, + parameter NBITS_Z = 38, + + parameter [2:0] OUTPUT_SELECT = 3'b0, + parameter [0:0] SATURATE_ENABLE = 1'b0, + parameter [5:0] SHIFT_RIGHT = 6'b0, + parameter [0:0] ROUND = 1'b0, + parameter [0:0] REGISTER_INPUTS = 1'b0 +)( + input wire [NBITS_A-1:0] a_i, + input wire [NBITS_B-1:0] b_i, + output wire [NBITS_Z-1:0] z_o, + output reg [NBITS_B-1:0] dly_b_o, + + input wire [5:0] acc_fir_i, + input wire [2:0] feedback_i, + input wire load_acc_i, + + input wire unsigned_a_i, + input wire unsigned_b_i, + + input wire clock_i, + input wire s_reset, + + input wire subtract_i, + input wire [NBITS_A-1:0] coef_0_i, + input wire [NBITS_A-1:0] coef_1_i, + input wire [NBITS_A-1:0] coef_2_i, + input wire [NBITS_A-1:0] coef_3_i +); + +// FIXME: The version of Icarus Verilog from Conda seems not to recognize the +// $error macro. Disable this sanity check for now because of that. + + // Input registers + reg [NBITS_A-1:0] r_a; + reg [NBITS_B-1:0] r_b; + reg [5:0] r_acc_fir; + reg r_unsigned_a; + reg r_unsigned_b; + reg r_load_acc; + reg [2:0] r_feedback; + reg [5:0] r_shift_d1; + reg [5:0] r_shift_d2; + reg r_subtract; + reg r_sat; + reg r_rnd; + reg [NBITS_ACC-1:0] acc; + + initial begin + r_a <= 0; + r_b <= 0; + + r_acc_fir <= 0; + r_unsigned_a <= 0; + r_unsigned_b <= 0; + r_feedback <= 0; + r_shift_d1 <= 0; + r_shift_d2 <= 0; + r_subtract <= 0; + r_load_acc <= 0; + r_sat <= 0; + r_rnd <= 0; + end + + always @(posedge clock_i or posedge s_reset) begin + if (s_reset) begin + + r_a <= 'h0; + r_b <= 'h0; + + r_acc_fir <= 0; + r_unsigned_a <= 0; + r_unsigned_b <= 0; + r_feedback <= 0; + r_shift_d1 <= 0; + r_shift_d2 <= 0; + r_subtract <= 0; + r_load_acc <= 0; + r_sat <= 0; + r_rnd <= 0; + + end else begin + + r_a <= a_i; + r_b <= b_i; + + r_acc_fir <= acc_fir_i; + r_unsigned_a <= unsigned_a_i; + r_unsigned_b <= unsigned_b_i; + r_feedback <= feedback_i; + r_shift_d1 <= SHIFT_RIGHT; + r_shift_d2 <= r_shift_d1; + r_subtract <= subtract_i; + r_load_acc <= load_acc_i; + r_sat <= r_sat; + r_rnd <= r_rnd; + + end + end + + // Registered / non-registered input path select + wire [NBITS_A-1:0] a = REGISTER_INPUTS ? r_a : a_i; + wire [NBITS_B-1:0] b = REGISTER_INPUTS ? r_b : b_i; + + wire [5:0] acc_fir = REGISTER_INPUTS ? r_acc_fir : acc_fir_i; + wire unsigned_a = REGISTER_INPUTS ? r_unsigned_a : unsigned_a_i; + wire unsigned_b = REGISTER_INPUTS ? r_unsigned_b : unsigned_b_i; + wire [2:0] feedback = REGISTER_INPUTS ? r_feedback : feedback_i; + wire load_acc = REGISTER_INPUTS ? r_load_acc : load_acc_i; + wire subtract = REGISTER_INPUTS ? r_subtract : subtract_i; + wire sat = REGISTER_INPUTS ? r_sat : SATURATE_ENABLE; + wire rnd = REGISTER_INPUTS ? r_rnd : ROUND; + + // Shift right control + wire [5:0] shift_d1 = REGISTER_INPUTS ? r_shift_d1 : SHIFT_RIGHT; + wire [5:0] shift_d2 = OUTPUT_SELECT[1] ? shift_d1 : r_shift_d2; + + // Multiplier + wire unsigned_mode = unsigned_a & unsigned_b; + wire [NBITS_A-1:0] mult_a; + assign mult_a = (feedback == 3'h0) ? a : + (feedback == 3'h1) ? a : + (feedback == 3'h2) ? a : + (feedback == 3'h3) ? acc[NBITS_A-1:0] : + (feedback == 3'h4) ? coef_0_i : + (feedback == 3'h5) ? coef_1_i : + (feedback == 3'h6) ? coef_2_i : + coef_3_i; // if feedback == 3'h7 + + wire [NBITS_B-1:0] mult_b = (feedback == 2'h2) ? {NBITS_B{1'b0}} : b; + + wire [NBITS_A-1:0] mult_sgn_a = mult_a[NBITS_A-1]; + wire [NBITS_A-1:0] mult_mag_a = (mult_sgn_a && !unsigned_a) ? (~mult_a + 1) : mult_a; + wire [NBITS_B-1:0] mult_sgn_b = mult_b[NBITS_B-1]; + wire [NBITS_B-1:0] mult_mag_b = (mult_sgn_b && !unsigned_b) ? (~mult_b + 1) : mult_b; + + wire [NBITS_A+NBITS_B-1:0] mult_mag = mult_mag_a * mult_mag_b; + wire mult_sgn = (mult_sgn_a && !unsigned_a) ^ (mult_sgn_b && !unsigned_b); + + wire [NBITS_A+NBITS_B-1:0] mult = (unsigned_a && unsigned_b) ? + (mult_a * mult_b) : (mult_sgn ? (~mult_mag + 1) : mult_mag); + + // Sign extension + wire [NBITS_ACC-1:0] mult_xtnd = unsigned_mode ? + {{(NBITS_ACC-NBITS_A-NBITS_B){1'b0}}, mult[NBITS_A+NBITS_B-1:0]} : + {{(NBITS_ACC-NBITS_A-NBITS_B){mult[NBITS_A+NBITS_B-1]}}, mult[NBITS_A+NBITS_B-1:0]}; + + // Adder + wire [NBITS_ACC-1:0] acc_fir_int = unsigned_a ? {{(NBITS_ACC-NBITS_A){1'b0}}, a} : + {{(NBITS_ACC-NBITS_A){a[NBITS_A-1]}}, a} ; + + wire [NBITS_ACC-1:0] add_a = (subtract) ? (~mult_xtnd + 1) : mult_xtnd; + wire [NBITS_ACC-1:0] add_b = (feedback_i == 3'h0) ? acc : + (feedback_i == 3'h1) ? {{NBITS_ACC}{1'b0}} : (acc_fir_int << acc_fir); + + wire [NBITS_ACC-1:0] add_o = add_a + add_b; + + // Accumulator + initial acc <= 0; + + always @(posedge clock_i or posedge s_reset) + if (s_reset) acc <= 'h0; + else begin + if (load_acc) + acc <= add_o; + else + acc <= acc; + end + + // Adder/accumulator output selection + wire [NBITS_ACC-1:0] acc_out = (OUTPUT_SELECT[1]) ? add_o : acc; + + // Round, shift, saturate + wire [NBITS_ACC-1:0] acc_rnd = (rnd && (SHIFT_RIGHT != 0)) ? (acc_out + ({{(NBITS_ACC-1){1'b0}}, 1'b1} << (SHIFT_RIGHT - 1))) : + acc_out; + + wire [NBITS_ACC-1:0] acc_shr = (unsigned_mode) ? (acc_rnd >> SHIFT_RIGHT) : + (acc_rnd >>> SHIFT_RIGHT); + + wire [NBITS_ACC-1:0] acc_sat_u = (acc_shr[NBITS_ACC-1:NBITS_Z] != 0) ? {{(NBITS_ACC-NBITS_Z){1'b0}},{NBITS_Z{1'b1}}} : + {{(NBITS_ACC-NBITS_Z){1'b0}},{acc_shr[NBITS_Z-1:0]}}; + + wire [NBITS_ACC-1:0] acc_sat_s = ((|acc_shr[NBITS_ACC-1:NBITS_Z-1] == 1'b0) || + (&acc_shr[NBITS_ACC-1:NBITS_Z-1] == 1'b1)) ? {{(NBITS_ACC-NBITS_Z){1'b0}},{acc_shr[NBITS_Z-1:0]}} : + {{(NBITS_ACC-NBITS_Z){1'b0}},{acc_shr[NBITS_ACC-1],{NBITS_Z-1{~acc_shr[NBITS_ACC-1]}}}}; + + wire [NBITS_ACC-1:0] acc_sat = (sat) ? ((unsigned_mode) ? acc_sat_u : acc_sat_s) : acc_shr; + + // Output signals + wire [NBITS_Z-1:0] z0; + reg [NBITS_Z-1:0] z1; + wire [NBITS_Z-1:0] z2; + + assign z0 = mult_xtnd[NBITS_Z-1:0]; + assign z2 = acc_sat[NBITS_Z-1:0]; + + initial z1 <= 0; + + always @(posedge clock_i or posedge s_reset) + if (s_reset) + z1 <= 0; + else begin + z1 <= (OUTPUT_SELECT == 3'b100) ? z0 : z2; + end + + // Output mux + assign z_o = (OUTPUT_SELECT == 3'h0) ? z0 : + (OUTPUT_SELECT == 3'h1) ? z2 : + (OUTPUT_SELECT == 3'h2) ? z2 : + (OUTPUT_SELECT == 3'h3) ? z2 : + (OUTPUT_SELECT == 3'h4) ? z1 : + (OUTPUT_SELECT == 3'h5) ? z1 : + (OUTPUT_SELECT == 3'h6) ? z1 : + z1; // if OUTPUT_SELECT == 3'h7 + + // B input delayed passthrough + initial dly_b_o <= 0; + + always @(posedge clock_i or posedge s_reset) + if (s_reset) + dly_b_o <= 0; + else + dly_b_o <= b_i; + +endmodule diff --git a/techlibs/quicklogic/synth_quicklogic.cc b/techlibs/quicklogic/synth_quicklogic.cc index d2df6bcff..969209190 100644 --- a/techlibs/quicklogic/synth_quicklogic.cc +++ b/techlibs/quicklogic/synth_quicklogic.cc @@ -46,6 +46,15 @@ struct SynthQuickLogicPass : public ScriptPass { log(" - pp3: PolarPro 3 \n"); log(" - qlf_k6n10f: K6N10f\n"); log("\n"); + log(" -nodsp\n"); + log(" do not use dsp_t1_* to implement multipliers and associated logic\n"); + log(" (qlf_k6n10f only).\n"); + log("\n"); + log(" -use_dsp_cfg_params\n"); + log(" By default use DSP blocks with configuration bits available at module\n"); + log(" ports. Specifying this forces usage of DSP block with configuration\n"); + log(" bits available as module parameters.\n"); + log("\n"); log(" -nocarry\n"); log(" do not use adder_carry cells in output netlist.\n"); log("\n"); @@ -74,7 +83,7 @@ struct SynthQuickLogicPass : public ScriptPass { } string top_opt, blif_file, edif_file, family, currmodule, verilog_file, lib_path; - bool abc9, inferAdder, nobram, bramTypes; + bool abc9, inferAdder, nobram, bramTypes, dsp; void clear_flags() override { @@ -89,6 +98,7 @@ struct SynthQuickLogicPass : public ScriptPass { nobram = false; bramTypes = false; lib_path = "+/quicklogic/"; + dsp = true; } void set_scratchpad_defaults(RTLIL::Design *design) { @@ -149,6 +159,14 @@ struct SynthQuickLogicPass : public ScriptPass { bramTypes = true; continue; } + if (args[argidx] == "-nodsp" || args[argidx] == "-no_dsp") { + dsp = false; + continue; + } + if (args[argidx] == "-use_dsp_cfg_params") { + use_dsp_cfg_params = " -use_dsp_cfg_params"; + continue; + } break; } extra_args(args, argidx, design); @@ -184,6 +202,8 @@ struct SynthQuickLogicPass : public ScriptPass { read_simlibs += stringf(" %sqlf_k6n10f/brams_sim.v", lib_path.c_str()); if (bramTypes) read_simlibs += stringf(" %sqlf_k6n10f/bram_types_sim.v", lib_path.c_str()); + if (dsp) + read_simlibs += stringf(" %sqlf_k6n10f/dsp_sim.v", lib_path.c_str()); } run(read_simlibs); run(stringf("hierarchy -check %s", help_mode ? "-top " : top_opt.c_str())); @@ -208,6 +228,24 @@ struct SynthQuickLogicPass : public ScriptPass { run("share"); } + if (check_label("map_dsp", "(for qlf_k6n10f, skip if -nodsp)") + && ((dsp && family == "qlf_k6n10f") || help_mode)) { + run("wreduce t:$mul"); + run("ql_dsp_macc" + use_dsp_cfg_params); + + run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=20 -D DSP_B_MAXWIDTH=18 -D DSP_A_MINWIDTH=11 -D DSP_B_MINWIDTH=10 -D DSP_NAME=$__QL_MUL20X18"); + run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=10 -D DSP_B_MAXWIDTH=9 -D DSP_A_MINWIDTH=4 -D DSP_B_MINWIDTH=4 -D DSP_NAME=$__QL_MUL10X9"); + run("chtype -set $mul t:$__soft_mul"); + + if (use_dsp_cfg_params.empty()) + run("techmap -map " + lib_path + family + "/dsp_map.v -D USE_DSP_CFG_PARAMS=0"); + else + run("techmap -map " + lib_path + family + "/dsp_map.v -D USE_DSP_CFG_PARAMS=1"); + run("ql_dsp_simd"); + run("techmap -map " + lib_path + family + "/dsp_final_map.v"); + run("ql_dsp_io_regs"); + } + if (check_label("coarse")) { run("techmap -map +/cmp2lut.v -D LUT_WIDTH=4"); run("opt_expr"); @@ -219,15 +257,16 @@ struct SynthQuickLogicPass : public ScriptPass { run("opt_clean"); } - if (check_label("map_bram", "(for qlf_k6n10f, skip if -no_bram)") && (help_mode || family == "qlf_k6n10f")) { + if (check_label("map_bram", "(for qlf_k6n10f, skip if -no_bram)")) { + if(family == "qlf_k6n10f" || help_mode) run("memory_libmap -lib " + lib_path + family + "/libmap_brams.txt"); run("ql_bram_merge"); run("techmap -map " + lib_path + family + "/libmap_brams_map.v"); run("techmap -autoproc -map " + lib_path + family + "/brams_map.v"); run("techmap -map " + lib_path + family + "/brams_final_map.v"); - if (help_mode || bramTypes) { - run("ql_bram_types"); + if (bramTypes || help_mode) { + run("ql_bram_types", "(if -bramtypes)"); } }