riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Various small fixes (from gcc compiler warnings)

This commit is contained in:
Clifford Wolf 2014-07-23 20:45:27 +02:00
parent c094c53de8
commit 20a7965f61
2 changed files with 5 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
frontends/ast/simplify.cc
View File

@ -2259,7 +2259,7 @@ AstNode *AstNode::eval_const_function(AstNode *fcall)
log_error("Non-constant range in %s:%d (called from %s:%d).\n",
range->filename.c_str(), range->linenum, fcall->filename.c_str(), fcall->linenum);
int offset = std::min(range->range_left, range->range_right);
int width = std::min(std::abs(range->range_left - range->range_right) + 1, width);
int width = std::abs(range->range_left - range->range_right) + 1;
varinfo_t &v = variables[stmt->children.at(0)->str];
RTLIL::Const r = stmt->children.at(1)->bitsAsConst(v.val.bits.size());
for (int i = 0; i < width; i++)

8
passes/fsm/fsmdata.h
View File

@ -143,25 +143,25 @@ struct FsmData
log(" Input signals:\n");
RTLIL::SigSpec sig_in = cell->connections["\\CTRL_IN"];
for (int i = 0; i < SIZE(sig_in); i++)
log(" %3zd: %s\n", i, log_signal(sig_in[i]));
log(" %3d: %s\n", i, log_signal(sig_in[i]));
log("\n");
log(" Output signals:\n");
RTLIL::SigSpec sig_out = cell->connections["\\CTRL_OUT"];
for (int i = 0; i < SIZE(sig_out); i++)
log(" %3zd: %s\n", i, log_signal(sig_out[i]));
log(" %3d: %s\n", i, log_signal(sig_out[i]));
log("\n");
log(" State encoding:\n");
for (int i = 0; i < SIZE(state_table); i++)
log(" %3zd: %10s%s\n", i, log_signal(state_table[i], false),
log(" %3d: %10s%s\n", i, log_signal(state_table[i], false),
int(i) == reset_state ? " <RESET STATE>" : "");
log("\n");
log(" Transition Table (state_in, ctrl_in, state_out, ctrl_out):\n");
for (int i = 0; i < SIZE(transition_table); i++) {
transition_t &tr = transition_table[i];
log(" %5zd: %5d %s -> %5d %s\n", i, tr.state_in, log_signal(tr.ctrl_in), tr.state_out, log_signal(tr.ctrl_out));
log(" %5d: %5d %s -> %5d %s\n", i, tr.state_in, log_signal(tr.ctrl_in), tr.state_out, log_signal(tr.ctrl_out));
}
log("\n");