mirror of https://github.com/YosysHQ/yosys.git
Various small fixes (from gcc compiler warnings)
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c094c53de8
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@ -2259,7 +2259,7 @@ AstNode *AstNode::eval_const_function(AstNode *fcall)
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log_error("Non-constant range in %s:%d (called from %s:%d).\n",
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log_error("Non-constant range in %s:%d (called from %s:%d).\n",
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range->filename.c_str(), range->linenum, fcall->filename.c_str(), fcall->linenum);
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range->filename.c_str(), range->linenum, fcall->filename.c_str(), fcall->linenum);
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int offset = std::min(range->range_left, range->range_right);
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int offset = std::min(range->range_left, range->range_right);
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int width = std::min(std::abs(range->range_left - range->range_right) + 1, width);
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int width = std::abs(range->range_left - range->range_right) + 1;
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varinfo_t &v = variables[stmt->children.at(0)->str];
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varinfo_t &v = variables[stmt->children.at(0)->str];
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RTLIL::Const r = stmt->children.at(1)->bitsAsConst(v.val.bits.size());
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RTLIL::Const r = stmt->children.at(1)->bitsAsConst(v.val.bits.size());
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for (int i = 0; i < width; i++)
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for (int i = 0; i < width; i++)
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@ -143,25 +143,25 @@ struct FsmData
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log(" Input signals:\n");
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log(" Input signals:\n");
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RTLIL::SigSpec sig_in = cell->connections["\\CTRL_IN"];
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RTLIL::SigSpec sig_in = cell->connections["\\CTRL_IN"];
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for (int i = 0; i < SIZE(sig_in); i++)
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for (int i = 0; i < SIZE(sig_in); i++)
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log(" %3zd: %s\n", i, log_signal(sig_in[i]));
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log(" %3d: %s\n", i, log_signal(sig_in[i]));
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log("\n");
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log("\n");
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log(" Output signals:\n");
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log(" Output signals:\n");
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RTLIL::SigSpec sig_out = cell->connections["\\CTRL_OUT"];
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RTLIL::SigSpec sig_out = cell->connections["\\CTRL_OUT"];
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for (int i = 0; i < SIZE(sig_out); i++)
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for (int i = 0; i < SIZE(sig_out); i++)
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log(" %3zd: %s\n", i, log_signal(sig_out[i]));
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log(" %3d: %s\n", i, log_signal(sig_out[i]));
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log("\n");
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log("\n");
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log(" State encoding:\n");
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log(" State encoding:\n");
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for (int i = 0; i < SIZE(state_table); i++)
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for (int i = 0; i < SIZE(state_table); i++)
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log(" %3zd: %10s%s\n", i, log_signal(state_table[i], false),
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log(" %3d: %10s%s\n", i, log_signal(state_table[i], false),
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int(i) == reset_state ? " <RESET STATE>" : "");
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int(i) == reset_state ? " <RESET STATE>" : "");
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log("\n");
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log("\n");
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log(" Transition Table (state_in, ctrl_in, state_out, ctrl_out):\n");
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log(" Transition Table (state_in, ctrl_in, state_out, ctrl_out):\n");
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for (int i = 0; i < SIZE(transition_table); i++) {
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for (int i = 0; i < SIZE(transition_table); i++) {
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transition_t &tr = transition_table[i];
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transition_t &tr = transition_table[i];
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log(" %5zd: %5d %s -> %5d %s\n", i, tr.state_in, log_signal(tr.ctrl_in), tr.state_out, log_signal(tr.ctrl_out));
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log(" %5d: %5d %s -> %5d %s\n", i, tr.state_in, log_signal(tr.ctrl_in), tr.state_out, log_signal(tr.ctrl_out));
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}
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}
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log("\n");
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log("\n");
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