mirror of https://github.com/YosysHQ/yosys.git
fixup verilog doubleslash test
- add generated doubleslash.v to .gitignore - ensure backend verilog can be read again
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@ -3,3 +3,4 @@
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/run-test.mk
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/run-test.mk
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/const_arst.v
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/const_arst.v
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/const_sr.v
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/const_sr.v
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/doubleslash.v
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@ -17,3 +17,5 @@ proc
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opt -full
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opt -full
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write_verilog doubleslash.v
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write_verilog doubleslash.v
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design -reset
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read_verilog doubleslash.v
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