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Add "add -mod" 

Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2019-09-20 10:27:17 +02:00
parent db17833a5f
commit 1f64b34c64
1 changed files with 18 additions and 0 deletions
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18
passes/cmds/add.cc
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@ -105,6 +105,11 @@ struct AddPass : public Pass {
log("Like 'add -input', but also connect the signal between instances of the\n"); log("Like 'add -input', but also connect the signal between instances of the\n");
log("selected modules.\n"); log("selected modules.\n");
log("\n"); log("\n");
log("\n");
log(" add -mod <name[s]>\n");
log("\n");
log("Add module[s] with the specified name[s].\n");
log("\n");
} }
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{ {
@ -113,6 +118,7 @@ struct AddPass : public Pass {
bool arg_flag_input = false; bool arg_flag_input = false;
bool arg_flag_output = false; bool arg_flag_output = false;
bool arg_flag_global = false; bool arg_flag_global = false;
bool mod_mode = false;
int arg_width = 0; int arg_width = 0;
size_t argidx; size_t argidx;
@ -133,8 +139,20 @@ struct AddPass : public Pass {
arg_width = atoi(args[++argidx].c_str()); arg_width = atoi(args[++argidx].c_str());
continue; continue;
} }
if (arg == "-mod") {
mod_mode = true;
argidx++;
break;
}
break; break;
} }
if (mod_mode) {
for (; argidx < args.size(); argidx++)
design->addModule(RTLIL::escape_id(args[argidx]));
return;
}
extra_args(args, argidx, design); extra_args(args, argidx, design);
for (auto &mod : design->modules_) for (auto &mod : design->modules_)