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Merge pull request #802 from whitequark/write_verilog_async_mem_ports 

write_verilog: correctly emit asynchronous transparent ports
This commit is contained in:
Clifford Wolf 2019-02-12 14:41:34 +01:00 committed by GitHub
parent b9f6ed40b6 da65e1e8d9
commit 1f2548a564
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GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 41 additions and 38 deletions
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11
backends/verilog/verilog_backend.cc
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@ -1065,6 +1065,8 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
use_rd_clk = cell->parameters["\\RD_CLK_ENABLE"].extract(i).as_bool(); use_rd_clk = cell->parameters["\\RD_CLK_ENABLE"].extract(i).as_bool();
rd_clk_posedge = cell->parameters["\\RD_CLK_POLARITY"].extract(i).as_bool(); rd_clk_posedge = cell->parameters["\\RD_CLK_POLARITY"].extract(i).as_bool();
rd_transparent = cell->parameters["\\RD_TRANSPARENT"].extract(i).as_bool(); rd_transparent = cell->parameters["\\RD_TRANSPARENT"].extract(i).as_bool();
if (use_rd_clk)
{
{ {
std::ostringstream os; std::ostringstream os;
dump_sigspec(os, sig_rd_clk); dump_sigspec(os, sig_rd_clk);
@ -1072,7 +1074,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
if( clk_to_lof_body.count(clk_domain_str) == 0 ) if( clk_to_lof_body.count(clk_domain_str) == 0 )
clk_to_lof_body[clk_domain_str] = std::vector<std::string>(); clk_to_lof_body[clk_domain_str] = std::vector<std::string>();
} }
if (use_rd_clk && !rd_transparent) if (!rd_transparent)
{ {
// for clocked read ports make something like: // for clocked read ports make something like:
// reg [..] temp_id; // reg [..] temp_id;
@ -1100,8 +1102,9 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
std::string line = stringf("assign %s = %s;\n", os.str().c_str(), temp_id.c_str()); std::string line = stringf("assign %s = %s;\n", os.str().c_str(), temp_id.c_str());
clk_to_lof_body[""].push_back(line); clk_to_lof_body[""].push_back(line);
} }
} else { }
if (rd_transparent) { else
{
// for rd-transparent read-ports make something like: // for rd-transparent read-ports make something like:
// reg [..] temp_id; // reg [..] temp_id;
// always @(posedge clk) // always @(posedge clk)
@ -1121,6 +1124,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
std::string line = stringf("assign %s = %s[%s];\n", os.str().c_str(), mem_id.c_str(), temp_id.c_str()); std::string line = stringf("assign %s = %s[%s];\n", os.str().c_str(), mem_id.c_str(), temp_id.c_str());
clk_to_lof_body[""].push_back(line); clk_to_lof_body[""].push_back(line);
} }
}
} else { } else {
// for non-clocked read-ports make something like: // for non-clocked read-ports make something like:
// assign r_data = array_reg[r_addr]; // assign r_data = array_reg[r_addr];
@ -1131,7 +1135,6 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
clk_to_lof_body[""].push_back(line); clk_to_lof_body[""].push_back(line);
} }
} }
}
int nwrite_ports = cell->parameters["\\WR_PORTS"].as_int(); int nwrite_ports = cell->parameters["\\WR_PORTS"].as_int();
RTLIL::SigSpec sig_wr_clk, sig_wr_data, sig_wr_addr, sig_wr_en; RTLIL::SigSpec sig_wr_clk, sig_wr_data, sig_wr_addr, sig_wr_en;