mirror of https://github.com/YosysHQ/yosys.git
Add support for overflow using pattern detector
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@ -271,6 +271,7 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
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log("postAdd: %s\n", log_id(st.postAdd, "--"));
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log("postAdd: %s\n", log_id(st.postAdd, "--"));
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log("postAddMux: %s\n", log_id(st.postAddMux, "--"));
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log("postAddMux: %s\n", log_id(st.postAddMux, "--"));
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log("ffP: %s %s %s\n", log_id(st.ffP, "--"), log_id(st.ffPcemux, "--"), log_id(st.ffPrstmux, "--"));
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log("ffP: %s %s %s\n", log_id(st.ffP, "--"), log_id(st.ffPcemux, "--"), log_id(st.ffPrstmux, "--"));
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log("overflow: %s\n", log_id(st.overflow, "--"));
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#endif
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#endif
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log("Analysing %s.%s for Xilinx DSP packing.\n", log_id(pm.module), log_id(st.dsp));
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log("Analysing %s.%s for Xilinx DSP packing.\n", log_id(pm.module), log_id(st.dsp));
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@ -329,6 +330,24 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
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pm.autoremove(st.postAdd);
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pm.autoremove(st.postAdd);
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}
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}
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if (st.overflow) {
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log(" overflow %s (%s)\n", log_id(st.overflow), log_id(st.overflow->type));
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cell->setParam("\\USE_PATTERN_DETECT", Const("PATDET"));
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cell->setParam("\\SEL_PATTERN", Const("PATTERN"));
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cell->setParam("\\SEL_MASK", Const("MASK"));
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if (st.overflow->type == "$ge") {
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int B = st.overflow->getPort("\\B").as_int();
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log_assert((B & (B-1)) == 0); // Exact power of 2
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cell->setParam("\\MASK", Const(B-1, 48));
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cell->setParam("\\PATTERN", Const(0, 48));
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cell->setPort("\\OVERFLOW", st.overflow->getPort("\\Y"));
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}
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else log_abort();
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pm.autoremove(st.overflow);
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}
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if (st.clock != SigBit())
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if (st.clock != SigBit())
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{
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{
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@ -264,7 +264,6 @@ match postAdd
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select postAdd->type.in($add)
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select postAdd->type.in($add)
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select GetSize(port(postAdd, \Y)) <= 48
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select GetSize(port(postAdd, \Y)) <= 48
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select nusers(port(postAdd, \Y)) == 2
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choice <IdString> AB {\A, \B}
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choice <IdString> AB {\A, \B}
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select nusers(port(postAdd, AB)) <= 3
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select nusers(port(postAdd, AB)) <= 3
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filter ffMcemux || nusers(port(postAdd, AB)) == 2
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filter ffMcemux || nusers(port(postAdd, AB)) == 2
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@ -356,6 +355,18 @@ code argQ ffC ffCcemux ffCrstmux ffCcepol ffCrstpol sigC clock
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}
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}
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endcode
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endcode
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match overflow
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if ffP
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if dsp->parameters.at(\USE_PATTERN_DETECT, Const("NO_PATDET")).decode_string() == "NO_PATDET"
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select overflow->type.in($ge)
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select GetSize(port(overflow, \Y)) <= 48
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select port(overflow, \B).is_fully_const()
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// Check is exact power of 2
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select (port(overflow, \B).as_int() & (port(overflow, \B).as_int()-1)) == 0
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index <SigSpec> port(overflow, \A) === sigP
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optional
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endmatch
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code
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code
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accept;
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accept;
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endcode
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endcode
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