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Fix tests/various/specify.v 

Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2019-07-03 11:25:05 +02:00
parent ba36567908
commit 1f173210eb
2 changed files with 3 additions and 8 deletions
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9
tests/various/specify.v
View File

@ -7,9 +7,11 @@ module test (
if (EN) Q <= D; if (EN) Q <= D;
specify specify
`ifndef SKIP_UNSUPPORTED_IGN_PARSER_CONSTRUCTS
if (EN) (posedge CLK *> (Q : D)) = (1, 2:3:4); if (EN) (posedge CLK *> (Q : D)) = (1, 2:3:4);
$setup(D, posedge CLK &&& EN, 5); $setup(D, posedge CLK &&& EN, 5);
$hold(posedge CLK, D &&& EN, 6); $hold(posedge CLK, D &&& EN, 6);
`endif
endspecify endspecify
endmodule endmodule
@ -31,14 +33,7 @@ endmodule
module issue01144(input clk, d, output q); module issue01144(input clk, d, output q);
specify specify
// Fails:
(posedge clk => (q +: d)) = (3,1); (posedge clk => (q +: d)) = (3,1);
//(/*posedge*/ clk => (q +: d)) = (3,1); // Invalid syntax
(posedge clk *> (q +: d)) = (3,1); (posedge clk *> (q +: d)) = (3,1);
//(/*posedge*/ clk *> (q +: d)) = (3,1); // Invalid syntax
// Works:
(/*posedge*/ clk => q) = (3,1);
(/*posedge*/ clk *> q) = (3,1);
endspecify endspecify
endmodule endmodule

2
tests/various/specify.ys
View File

@ -55,4 +55,4 @@ equiv_induct -seq 5
equiv_status -assert equiv_status -assert
design -reset design -reset
read_verilog specify.v read_verilog -DSKIP_UNSUPPORTED_IGN_PARSER_CONSTRUCTS specify.v