riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

coolrunner2: Add FFs with clock enable to cells_sim.v

This commit is contained in:
Robert Ou 2017-08-01 11:58:01 -07:00 committed by Andrew Zonenberg
parent 007f29b9c2
commit 1e3ffd57cb
1 changed files with 60 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

60
techlibs/coolrunner2/cells_sim.v
View File

@ -244,3 +244,63 @@ module FTDCP (C, PRE, CLR, T, Q);
assign Q = Q_; assign Q = Q_;
endmodule endmodule
module FDCPE (C, PRE, CLR, D, Q, CE);
parameter INIT = 0;
input C, PRE, CLR, D, CE;
output reg Q;
initial begin
Q <= INIT;
end
always @(posedge C, posedge PRE, posedge CLR) begin
if (CLR == 1)
Q <= 0;
else if (PRE == 1)
Q <= 1;
else if (CE == 1)
Q <= D;
end
endmodule
module FDCPE_N (C, PRE, CLR, D, Q, CE);
parameter INIT = 0;
input C, PRE, CLR, D, CE;
output reg Q;
initial begin
Q <= INIT;
end
always @(negedge C, posedge PRE, posedge CLR) begin
if (CLR == 1)
Q <= 0;
else if (PRE == 1)
Q <= 1;
else if (CE == 1)
Q <= D;
end
endmodule
module FDDCPE (C, PRE, CLR, D, Q, CE);
parameter INIT = 0;
input C, PRE, CLR, D, CE;
output reg Q;
initial begin
Q <= INIT;
end
always @(posedge C, negedge C, posedge PRE, posedge CLR) begin
if (CLR == 1)
Q <= 0;
else if (PRE == 1)
Q <= 1;
else if (CE == 1)
Q <= D;
end
endmodule