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Added support for (single-clock) transparent memories to bram tests

This commit is contained in:
Clifford Wolf 2016-11-01 10:03:13 +01:00
parent d9d38eeedb
commit 1e3c2bff72
2 changed files with 23 additions and 10 deletions
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31
tests/bram/generate.py
View File

@ -25,12 +25,15 @@ def create_bram(dsc_f, sim_f, ref_f, tb_f, k1, k2, or_next):
if wrmode.count(0) == 0: continue if wrmode.count(0) == 0: continue
break break
if random.randrange(2) or True: if random.randrange(2):
maxpol = 4 maxpol = 4
maxtransp = 1 maxtransp = 1
maxclocks = 4
else: else:
maxpol = 2 maxpol = None
clkpol = random.randrange(4)
maxtransp = 2 maxtransp = 2
maxclocks = 1
def generate_enable(i): def generate_enable(i):
if wrmode[i]: if wrmode[i]:
@ -45,11 +48,16 @@ def create_bram(dsc_f, sim_f, ref_f, tb_f, k1, k2, or_next):
return random.randrange(maxtransp) return random.randrange(maxtransp)
return 0 return 0
ports = [ random.randrange(1, 3) for i in range(groups) ] def generate_clkpol(i):
enable = [ generate_enable(i) for i in range(groups) ] if maxpol is None:
transp = [ generate_transp(i) for i in range(groups) ] return clkpol
clocks = [ random.randrange(1, 4) for i in range(groups) ] return random.randrange(maxpol)
clkpol = [ random.randrange(maxpol) for i in range(groups) ]
ports = [ random.randrange(1, 3) for i in range(groups) ]
enable = [ generate_enable(i) for i in range(groups) ]
transp = [ generate_transp(i) for i in range(groups) ]
clocks = [ random.randrange(maxclocks)+1 for i in range(groups) ]
clkpol = [ generate_clkpol(i) for i in range(groups) ]
break break
print("bram bram_%02d_%02d" % (k1, k2), file=dsc_f) print("bram bram_%02d_%02d" % (k1, k2), file=dsc_f)
@ -109,11 +117,13 @@ def create_bram(dsc_f, sim_f, ref_f, tb_f, k1, k2, or_next):
if clocks[p1] and not ("CLK%d" % clocks[p1]) in v_ports: if clocks[p1] and not ("CLK%d" % clocks[p1]) in v_ports:
v_ports.add("CLK%d" % clocks[p1]) v_ports.add("CLK%d" % clocks[p1])
v_stmts.append("input CLK%d;" % clocks[p1]) v_stmts.append("input CLK%d;" % clocks[p1])
tb_decls.append("reg CLK%d;" % clocks[p1]) tb_decls.append("reg CLK%d = 0;" % clocks[p1])
tb_clocks.append("CLK%d" % clocks[p1]) tb_clocks.append("CLK%d" % clocks[p1])
v_ports.add("%sADDR" % pf) v_ports.add("%sADDR" % pf)
v_stmts.append("input [%d:0] %sADDR;" % (abits-1, pf)) v_stmts.append("input [%d:0] %sADDR;" % (abits-1, pf))
if transp[p1]:
v_stmts.append("reg [%d:0] %sADDR_Q;" % (abits-1, pf))
tb_decls.append("reg [%d:0] %sADDR;" % (abits-1, pf)) tb_decls.append("reg [%d:0] %sADDR;" % (abits-1, pf))
tb_addr.append("%sADDR" % pf) tb_addr.append("%sADDR" % pf)
@ -159,8 +169,11 @@ def create_bram(dsc_f, sim_f, ref_f, tb_f, k1, k2, or_next):
for i in range(enable[p1]): for i in range(enable[p1]):
enrange = "[%d:%d]" % ((i+1)*dbits/enable[p1]-1, i*dbits/enable[p1]) enrange = "[%d:%d]" % ((i+1)*dbits/enable[p1]-1, i*dbits/enable[p1])
v_always[last_always_hdr].append((portindex, pf, "if (%sEN[%d]) memory[%sADDR]%s = %sDATA%s;" % (pf, i, pf, enrange, pf, enrange))) v_always[last_always_hdr].append((portindex, pf, "if (%sEN[%d]) memory[%sADDR]%s = %sDATA%s;" % (pf, i, pf, enrange, pf, enrange)))
elif transp[p1]:
v_always[last_always_hdr].append((sum(ports)+1, pf, "%sADDR_Q %s %sADDR;" % (pf, assign_op, pf)))
v_stmts.append("always @* %sDATA = memory[%sADDR_Q];" % (pf, pf))
else: else:
v_always[last_always_hdr].append((sum(ports)+1 if transp[p1] else 0, pf, "%sDATA %s memory[%sADDR];" % (pf, assign_op, pf))) v_always[last_always_hdr].append((0, pf, "%sDATA %s memory[%sADDR];" % (pf, assign_op, pf)))
for always_hdr in sorted(v_always): for always_hdr in sorted(v_always):
v_stmts.append(always_hdr[1]) v_stmts.append(always_hdr[1])

2
tests/bram/run-test.sh
View File

@ -9,7 +9,7 @@ OPTIND=1
count=5 count=5
seed="" # default to no seed specified seed="" # default to no seed specified
debug="" debug=""
while getopts "c:S:" opt while getopts "c:dS:" opt
do do
case "$opt" in case "$opt" in
c) count="$OPTARG" ;; c) count="$OPTARG" ;;