Merge remote-tracking branch 'origin/master' into xc7mux

CHANGELOG

@@ -16,7 +16,11 @@ Yosys 0.8 .. Yosys 0.8-dev
     - Added "gate2lut.v" techmap rule
     - Added "rename -src"
     - Added "equiv_opt" pass
+<<<<<<< HEAD
     - Added "muxpack" pass
+=======
+    - Added "read_aiger" frontend
+>>>>>>> origin/master
     - "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx"
 
 

frontends/aiger/aigerparse.cc

@@ -85,11 +85,26 @@ end_of_header:
 	else
 		log_abort();
 
+	RTLIL::Wire* n0 = module->wire("\\n0");
+	if (n0)
+		module->connect(n0, RTLIL::S0);
+
+	for (unsigned i = 0; i < outputs.size(); ++i) {
+		RTLIL::Wire *wire = outputs[i];
+		if (wire->port_input) {
+			RTLIL::Wire *o_wire = module->addWire(wire->name.str() + "_o");
+			o_wire->port_output = true;
+			wire->port_output = false;
+			module->connect(o_wire, wire);
+			outputs[i] = o_wire;
+		}
+	}
+
 	// Parse footer (symbol table, comments, etc.)
 	unsigned l1;
 	std::string s;
 	for (int c = f.peek(); c != EOF; c = f.peek(), ++line_count) {
-        if (c == 'i' || c == 'l' || c == 'o') {
+		if (c == 'i' || c == 'l' || c == 'o' || c == 'b') {
 			f.ignore(1);
 			if (!(f >> l1 >> s))
 				log_error("Line %u cannot be interpreted as a symbol entry!\n", line_count);
@@ -101,11 +116,12 @@ end_of_header:
 			if (c == 'i') wire = inputs[l1];
 			else if (c == 'l') wire = latches[l1];
 			else if (c == 'o') wire = outputs[l1];
+			else if (c == 'b') wire = bad_properties[l1];
 			else log_abort();
 
 			module->rename(wire, stringf("\\%s", s.c_str()));
 		}
-        else if (c == 'b' || c == 'j' || c == 'f') {
+		else if (c == 'j' || c == 'f') {
 			// TODO
 		}
 		else if (c == 'c') {
@@ -312,7 +328,7 @@ void AigerReader::parse_aiger_ascii()
 	unsigned l1, l2, l3;
 
 	// Parse inputs
-    for (unsigned i = 0; i < I; ++i, ++line_count) {
+	for (unsigned i = 1; i <= I; ++i, ++line_count) {
 		if (!(f >> l1))
 			log_error("Line %u cannot be interpreted as an input!\n", line_count);
 		log_debug("%d is an input\n", l1);
@@ -348,17 +364,19 @@ void AigerReader::parse_aiger_ascii()
 			if (!(f >> l3))
 				log_error("Line %u cannot be interpreted as a latch!\n", line_count);
 
-            if (l3 == 0 || l3 == 1)
-                q_wire->attributes["\\init"] = RTLIL::Const(l3);
+			if (l3 == 0)
+				q_wire->attributes["\\init"] = RTLIL::S0;
+			else if (l3 == 1)
+				q_wire->attributes["\\init"] = RTLIL::S1;
 			else if (l3 == l1) {
-                //q_wire->attributes["\\init"] = RTLIL::Const(RTLIL::State::Sx);
+				//q_wire->attributes["\\init"] = RTLIL::Sx;
 			}
 			else
 				log_error("Line %u has invalid reset literal for latch!\n", line_count);
 		}
 		else {
 			// AIGER latches are assumed to be initialized to zero
-            q_wire->attributes["\\init"] = RTLIL::Const(0);
+			q_wire->attributes["\\init"] = RTLIL::S0;
 		}
 		latches.push_back(q_wire);
 	}
@@ -397,11 +415,17 @@ void AigerReader::parse_aiger_ascii()
 		wire->port_output = true;
 		outputs.push_back(wire);
 	}
-    std::getline(f, line); // Ignore up to start of next line
 
-    // TODO: Parse bad state properties
-    for (unsigned i = 0; i < B; ++i, ++line_count)
-        std::getline(f, line); // Ignore up to start of next line
+	// Parse bad properties
+	for (unsigned i = 0; i < B; ++i, ++line_count) {
+		if (!(f >> l1))
+			log_error("Line %u cannot be interpreted as a bad state property!\n", line_count);
+
+		log_debug("%d is a bad state property\n", l1);
+		RTLIL::Wire *wire = createWireIfNotExists(module, l1);
+		wire->port_output = true;
+		bad_properties.push_back(wire);
+	}
 
 	// TODO: Parse invariant constraints
 	for (unsigned i = 0; i < C; ++i, ++line_count)
@@ -479,17 +503,19 @@ void AigerReader::parse_aiger_binary()
 			if (!(f >> l3))
 				log_error("Line %u cannot be interpreted as a latch!\n", line_count);
 
-            if (l3 == 0 || l3 == 1)
-                q_wire->attributes["\\init"] = RTLIL::Const(l3);
+			if (l3 == 0)
+				q_wire->attributes["\\init"] = RTLIL::S0;
+			else if (l3 == 1)
+				q_wire->attributes["\\init"] = RTLIL::S1;
 			else if (l3 == l1) {
-                //q_wire->attributes["\\init"] = RTLIL::Const(RTLIL::State::Sx);
+				//q_wire->attributes["\\init"] = RTLIL::Sx;
 			}
 			else
 				log_error("Line %u has invalid reset literal for latch!\n", line_count);
 		}
 		else {
 			// AIGER latches are assumed to be initialized to zero
-            q_wire->attributes["\\init"] = RTLIL::Const(0);
+			q_wire->attributes["\\init"] = RTLIL::S0;
 		}
 		latches.push_back(q_wire);
 	}
@@ -530,8 +556,17 @@ void AigerReader::parse_aiger_binary()
 	}
 	std::getline(f, line); // Ignore up to start of next line
 
-    // TODO: Parse bad state properties
-    for (unsigned i = 0; i < B; ++i, ++line_count)
+	// Parse bad properties
+	for (unsigned i = 0; i < B; ++i, ++line_count) {
+		if (!(f >> l1))
+			log_error("Line %u cannot be interpreted as a bad state property!\n", line_count);
+
+		log_debug("%d is a bad state property\n", l1);
+		RTLIL::Wire *wire = createWireIfNotExists(module, l1);
+		wire->port_output = true;
+		bad_properties.push_back(wire);
+	}
+	if (B > 0)
 		std::getline(f, line); // Ignore up to start of next line
 
 	// TODO: Parse invariant constraints

frontends/aiger/aigerparse.h

@@ -42,6 +42,7 @@ struct AigerReader
     std::vector<RTLIL::Wire*> inputs;
     std::vector<RTLIL::Wire*> latches;
     std::vector<RTLIL::Wire*> outputs;
+    std::vector<RTLIL::Wire*> bad_properties;
     std::vector<RTLIL::Cell*> boxes;
 
     AigerReader(RTLIL::Design *design, std::istream &f, RTLIL::IdString module_name, RTLIL::IdString clk_name, std::string map_filename, bool wideports);

frontends/ast/ast.cc

@@ -154,6 +154,7 @@ std::string AST::type2str(AstNodeType type)
 	X(AST_GENIF)
 	X(AST_GENCASE)
 	X(AST_GENBLOCK)
+	X(AST_TECALL)
 	X(AST_POSEDGE)
 	X(AST_NEGEDGE)
 	X(AST_EDGE)

frontends/ast/ast.h

@@ -137,6 +137,7 @@ namespace AST
 		AST_GENIF,
 		AST_GENCASE,
 		AST_GENBLOCK,
+		AST_TECALL,
 		
 		AST_POSEDGE,
 		AST_NEGEDGE,

frontends/ast/genrtlil.cc

@@ -1575,6 +1575,37 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 			delete always;
 		} break;
 
+	case AST_TECALL: {
+			int sz = children.size();
+			if (str == "$info") {
+				if (sz > 0)
+					log_file_info(filename, linenum, "%s.\n", children[0]->str.c_str());
+				else
+					log_file_info(filename, linenum, "\n");
+			} else if (str == "$warning") {
+				if (sz > 0)
+					log_file_warning(filename, linenum, "%s.\n", children[0]->str.c_str());
+				else
+					log_file_warning(filename, linenum, "\n");
+			} else if (str == "$error") {
+				if (sz > 0)
+					log_file_error(filename, linenum, "%s.\n", children[0]->str.c_str());
+				else
+					log_file_error(filename, linenum, "\n");
+			} else if (str == "$fatal") {
+				// TODO: 1st parameter, if exists, is 0,1 or 2, and passed to $finish()
+				// if no parameter is given, default value is 1
+				// dollar_finish(sz ? children[0] : 1);
+				// perhaps create & use log_file_fatal()
+				if (sz > 0)
+					log_file_error(filename, linenum, "FATAL: %s.\n", children[0]->str.c_str());
+				else
+					log_file_error(filename, linenum, "FATAL.\n");
+			} else {
+				log_file_error(filename, linenum, "Unknown elabortoon system task '%s'.\n", str.c_str());
+			}
+		} break;
+
 	case AST_FCALL: {
 			if (str == "\\$anyconst" || str == "\\$anyseq" || str == "\\$allconst" || str == "\\$allseq")
 			{

frontends/verilog/verilog_lexer.l

@@ -311,6 +311,11 @@ supply1 { return TOK_SUPPLY1; }
 	return TOK_ID;
 }
 
+"$"(info|warning|error|fatal) {
+	frontend_verilog_yylval.string = new std::string(yytext);
+	return TOK_ELAB_TASK;
+}
+
 "$signed"   { return TOK_TO_SIGNED; }
 "$unsigned" { return TOK_TO_UNSIGNED; }
 

frontends/verilog/verilog_parser.y

@@ -133,7 +133,7 @@ struct specify_rise_fall {
 }
 
 %token <string> TOK_STRING TOK_ID TOK_CONSTVAL TOK_REALVAL TOK_PRIMITIVE
-%token <string> TOK_SVA_LABEL TOK_SPECIFY_OPER
+%token <string> TOK_SVA_LABEL TOK_SPECIFY_OPER TOK_ELAB_TASK
 %token TOK_ASSERT TOK_ASSUME TOK_RESTRICT TOK_COVER TOK_FINAL
 %token ATTR_BEGIN ATTR_END DEFATTR_BEGIN DEFATTR_END
 %token TOK_MODULE TOK_ENDMODULE TOK_PARAMETER TOK_LOCALPARAM TOK_DEFPARAM
@@ -1557,6 +1557,15 @@ cell_port:
 		astbuf2->children.push_back(node);
 		delete $3;
 		free_attr($1);
+	} |
+	attr '.' TOK_ID {
+		AstNode *node = new AstNode(AST_ARGUMENT);
+		node->str = *$3;
+		astbuf2->children.push_back(node);
+		node->children.push_back(new AstNode(AST_IDENTIFIER));
+		node->children.back()->str = *$3;
+		delete $3;
+		free_attr($1);
 	};
 
 always_stmt:
@@ -2167,6 +2176,15 @@ gen_stmt:
 		if ($6 != NULL)
 			delete $6;
 		ast_stack.pop_back();
+	} |
+	TOK_ELAB_TASK {
+		AstNode *node = new AstNode(AST_TECALL);
+		node->str = *$1;
+		delete $1;
+		ast_stack.back()->children.push_back(node);
+		ast_stack.push_back(node);
+	} opt_arg_list ';'{
+		ast_stack.pop_back();		
 	};
 
 gen_stmt_block:

kernel/log.cc

@@ -282,6 +282,17 @@ void log_file_warning(const std::string &filename, int lineno,
 	va_end(ap);
 }
 
+void log_file_info(const std::string &filename, int lineno,
+                      const char *format, ...)
+{
+	va_list ap;
+	va_start(ap, format);
+	std::string fmt = stringf("%s:%d: Info: %s",
+			filename.c_str(), lineno, format);
+	logv(fmt.c_str(), ap);
+	va_end(ap);
+}
+
 YS_ATTRIBUTE(noreturn)
 static void logv_error_with_prefix(const char *prefix,
                                    const char *format, va_list ap)

kernel/log.h

@@ -80,6 +80,7 @@ void log_warning(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2));
 
 // Log with filename to report a problem in a source file.
 void log_file_warning(const std::string &filename, int lineno, const char *format, ...) YS_ATTRIBUTE(format(printf, 3, 4));
+void log_file_info(const std::string &filename, int lineno, const char *format, ...) YS_ATTRIBUTE(format(printf, 3, 4));
 
 void log_warning_noprefix(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2));
 YS_NORETURN void log_error(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2), noreturn);

misc/py_wrap_generator.py

@@ -2026,7 +2026,6 @@ def gen_wrappers(filename, debug_level_ = 0):
 #include <boost/python/wrapper.hpp>
 #include <boost/python/call.hpp>
 #include <boost/python.hpp>
-#include <boost/log/exceptions.hpp>
 
 USING_YOSYS_NAMESPACE
 

tests/aiger/and.aig

@@ -1,3 +0,0 @@
-aig 3 2 0 1 1
-6
-

tests/aiger/and_.aag

@@ -3,3 +3,6 @@ aag 3 2 0 1 1
 4
 6
 6 2 4
+i0 pi0
+i1 pi1
+o0 po0

tests/aiger/and_.aig

@@ -0,0 +1,5 @@
+aig 3 2 0 1 1
+6
+i0 pi0
+i1 pi1
+o0 po0

tests/aiger/buffer.aag

@@ -1,3 +1,5 @@
 aag 1 1 0 1 0
 2
 2
+i0 pi0
+o0 po0

tests/aiger/buffer.aig

@@ -1,2 +1,4 @@
 aig 1 1 0 1 0
 2
+i0 pi0
+o0 po0

tests/aiger/cnt1.aag

@@ -1,3 +1,4 @@
 aag 1 0 1 0 0 1
 2 3
 2
+b0 po0

tests/aiger/cnt1.aig

@@ -1,3 +1,4 @@
 aig 1 0 1 0 0 1
 3
 2
+b0 po0

tests/aiger/cnt1e.aag

@@ -6,3 +6,4 @@ aag 5 1 1 0 3 1
 8 4 2
 10 9 7
 b0 AIGER_NEVER
+i0 po0

tests/aiger/cnt1e.aig

@@ -1,4 +1,5 @@
 aig 5 1 1 0 3 1
 10
 4
-

b0 AIGER_NEVER
+

i0 po0
+b0 AIGER_NEVER

tests/aiger/false.aag

@@ -1,2 +1,3 @@
 aag 0 0 0 1 0
 0
+o0 po0

tests/aiger/false.aig

@@ -1,2 +1,3 @@
 aig 0 0 0 1 0
 0
+o0 po0

tests/aiger/inverter.aag

@@ -1,3 +1,5 @@
 aag 1 1 0 1 0
 2
 3
+i0 pi0
+o0 po0

tests/aiger/inverter.aig

@@ -1,2 +1,4 @@
 aig 1 1 0 1 0
 3
+i0 pi0
+o0 po0

tests/aiger/notcnt1e.aag

@@ -6,3 +6,4 @@ aag 5 1 1 0 3 1
 8 4 2
 10 9 7
 b0 AIGER_NEVER
+i0 pi0

tests/aiger/notcnt1e.aig

@@ -1,4 +1,5 @@
 aig 5 1 1 0 3 1
 10
 5
-

b0 AIGER_NEVER
+

i0 pi0
+b0 AIGER_NEVER

tests/aiger/or.aig

@@ -1,3 +0,0 @@
-aig 3 2 0 1 1
-7
-


tests/aiger/or_.aag

@@ -3,3 +3,6 @@ aag 3 2 0 1 1
 4
 7
 6 3 5
+i0 pi0
+i1 pi1
+o0 po0

tests/aiger/or_.aig

@@ -0,0 +1,5 @@
+aig 3 2 0 1 1
+7
+
i0 pi0
+i1 pi1
+o0 po0

tests/aiger/run-test.sh

@@ -1,24 +1,37 @@
 #!/bin/bash
 
-OPTIND=1
-seed=""    # default to no seed specified
-while getopts "S:" opt
-do
-    case "$opt" in
-	S) arg="${OPTARG#"${OPTARG%%[![:space:]]*}"}" # remove leading space
-	   seed="SEED=$arg" ;;
-    esac
+set -e
+
+for aag in *.aag; do
+    # Since ABC cannot read *.aag, read the *.aig instead
+    # (which would have been created by the reference aig2aig utility)
+    ../../yosys-abc -c "read -c ${aag%.*}.aig; write ${aag%.*}_ref.v"
+    ../../yosys -p "
+read_verilog ${aag%.*}_ref.v
+prep
+design -stash gold
+read_aiger -clk_name clock $aag
+prep
+design -stash gate
+design -import gold -as gold
+design -import gate -as gate
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports -seq 16 miter
+"
 done
-shift "$((OPTIND-1))"
 
-# check for Icarus Verilog
-if ! which iverilog > /dev/null ; then
-  echo "$0: Error: Icarus Verilog 'iverilog' not found."
-  exit 1
-fi
-
-echo "===== AAG ======"
-${MAKE:-make} -f ../tools/autotest.mk $seed *.aag EXTRA_FLAGS="-f aiger"
-
-echo "===== AIG ======"
-exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.aig EXTRA_FLAGS="-f aiger"
+for aig in *.aig; do
+    ../../yosys-abc -c "read -c $aig; write ${aig%.*}_ref.v"
+    ../../yosys -p "
+read_verilog ${aig%.*}_ref.v
+prep
+design -stash gold
+read_aiger -clk_name clock $aig
+prep
+design -stash gate
+design -import gold -as gold
+design -import gate -as gate
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports -seq 16 miter
+"
+done

tests/aiger/toggle.aag

@@ -2,3 +2,5 @@ aag 1 0 1 2 0
 2 3
 2
 3
+o0 po0
+o1 po1

tests/aiger/toggle.aig

@@ -2,3 +2,5 @@ aig 1 0 1 2 0
 3
 2
 3
+o0 po0
+o1 po1

tests/aiger/true.aag

@@ -1,2 +1,3 @@
 aag 0 0 0 1 0
 1
+o0 po0

tests/aiger/true.aig

@@ -1,2 +1,3 @@
 aig 0 0 0 1 0
 1
+o0 po0

tests/simple/implicit_ports.v

@@ -0,0 +1,16 @@
+// Test implicit port connections
+module alu (input [2:0] a, input [2:0] b, input cin, output cout, output [2:0] result);
+	assign cout = cin;
+	assign result = a + b;
+endmodule
+
+module named_ports(input [2:0] a, b, output [2:0] alu_result, output cout);
+	wire cin = 1;
+	alu alu (
+		.a(a),
+		.b, // Implicit connection is equivalent to .b(b)
+		.cin(), // Explicitely unconnected
+		.cout(cout),
+		.result(alu_result)
+	);
+endmodule

tests/simple/run-test.sh

@@ -17,4 +17,5 @@ if ! which iverilog > /dev/null ; then
   exit 1
 fi
 
-exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v
+shopt -s nullglob
+exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.{sv,v}

tests/tools/autotest.sh

@@ -89,6 +89,13 @@ done
 
 compile_and_run() {
 	exe="$1"; output="$2"; shift 2
+	ext=${1##*.}
+	if [ "$ext" == "sv" ]; then
+		language_gen="-g2012"
+	else
+		language_gen="-g2005"
+	fi
+
 	if $use_modelsim; then
 		altver=$( ls -v /opt/altera/ | grep '^[0-9]' | tail -n1; )
 		/opt/altera/$altver/modelsim_ase/bin/vlib work
@@ -99,7 +106,7 @@ compile_and_run() {
 		/opt/Xilinx/Vivado/$xilver/bin/xvlog $xinclude_opts -d outfile=\"$output\" "$@"
 		/opt/Xilinx/Vivado/$xilver/bin/xelab -R work.testbench
 	else
-		iverilog $include_opts -Doutfile=\"$output\" -s testbench -o "$exe" "$@"
+		iverilog $language_gen $include_opts -Doutfile=\"$output\" -s testbench -o "$exe" "$@"
 		vvp -n "$exe"
 	fi
 }
@@ -110,7 +117,7 @@ for fn
 do
 	bn=${fn%.*}
 	ext=${fn##*.}
-	if [[ "$ext" != "v" ]] && [[ "$ext" != "aag" ]] && [[ "$ext" != "aig" ]]; then
+	if [[ "$ext" != "v" ]] && [[ "$ext" != "sv" ]] && [[ "$ext" != "aag" ]] && [[ "$ext" != "aig" ]]; then
 		echo "Invalid argument: $fn" >&2
 		exit 1
 	fi
@@ -123,6 +130,10 @@ do
 		echo -n "Test: $bn "
 	fi
 
+	if [ "$ext" == sv ]; then
+		frontend="$frontend -sv"
+	fi
+
 	rm -f ${bn}.{err,log,skip}
 	mkdir -p ${bn}.out
 	rm -rf ${bn}.out/*
@@ -135,9 +146,10 @@ do
 		rm -f ${bn}_ref.fir
 		if [[ "$ext" == "v" ]]; then
 			egrep -v '^\s*`timescale' ../$fn > ${bn}_ref.${ext}
+		elif [[ "$ext" == "aig" ]] || [[ "$ext" == "aag" ]]; then
+			"$toolsdir"/../../yosys-abc -c "read_aiger ../${fn}; write ${bn}_ref.v"
 		else
-			"$toolsdir"/../../yosys -f "$frontend $include_opts" -b "verilog" -o ${bn}_ref.v ../${fn}
-			frontend="verilog -noblackbox"
+			cp ../${fn} ${bn}_ref.${ext}
 		fi
 
 		if [ ! -f ../${bn}_tb.v ]; then

tests/various/elab_sys_tasks.sv

@@ -0,0 +1,30 @@
+module test;
+localparam X=1;
+genvar i;
+generate
+if (X == 1)
+  $info("X is 1");
+if (X == 1)
+  $warning("X is 1");
+else
+  $error("X is not 1");
+case (X)
+  1: $info("X is 1 in a case statement");
+endcase
+//case (X-1)
+//  1: $warn("X is 2");
+//  default: $warn("X might be anything in a case statement");
+//endcase
+for (i = 0; i < 3; i = i + 1)
+begin
+  case(i)
+    0: $info;
+    1: $warning;
+    default: $info("default case statemnent");
+  endcase
+end
+
+$info("This is a standalone $info(). Next $info has no parameters");
+$info;
+endgenerate
+endmodule

tests/various/elab_sys_tasks.ys

@@ -0,0 +1 @@
+read_verilog -sv elab_sys_tasks.sv