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Reduce comparisons of size_t and int 

`Const::size()` returns int, so change iterators that use it to `auto` instead of `size_t`.
For cases where size is being explicitly cast to `int`, use the wrapper that we already have instead: `Yosys::GetSize()`.
This commit is contained in:
Krystine Sherwin 2024-11-29 12:31:34 +13:00
parent 6f3376cbe6
commit 1de5d98ae2
No known key found for this signature in database
9 changed files with 59 additions and 59 deletions
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2
backends/edif/edif.cc
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@ -338,7 +338,7 @@ struct EdifBackend : public Backend {
*f << stringf("\n (property %s (integer %u))", EDIF_DEF(name), val.as_int()); *f << stringf("\n (property %s (integer %u))", EDIF_DEF(name), val.as_int());
else { else {
std::string hex_string = ""; std::string hex_string = "";
for (size_t i = 0; i < val.size(); i += 4) { for (auto i = 0; i < val.size(); i += 4) {
int digit_value = 0; int digit_value = 0;
if (i+0 < val.size() && val.at(i+0) == RTLIL::State::S1) digit_value |= 1; if (i+0 < val.size() && val.at(i+0) == RTLIL::State::S1) digit_value |= 1;
if (i+1 < val.size() && val.at(i+1) == RTLIL::State::S1) digit_value |= 2; if (i+1 < val.size() && val.at(i+1) == RTLIL::State::S1) digit_value |= 2;

10
frontends/ast/ast.cc
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@ -931,7 +931,7 @@ bool AstNode::bits_only_01() const
RTLIL::Const AstNode::bitsAsUnsizedConst(int width) RTLIL::Const AstNode::bitsAsUnsizedConst(int width)
{ {
RTLIL::State extbit = bits.back(); RTLIL::State extbit = bits.back();
while (width > int(bits.size())) while (width > GetSize(bits))
bits.push_back(extbit); bits.push_back(extbit);
return RTLIL::Const(bits); return RTLIL::Const(bits);
} }
@ -939,13 +939,13 @@ RTLIL::Const AstNode::bitsAsUnsizedConst(int width)
RTLIL::Const AstNode::bitsAsConst(int width, bool is_signed) RTLIL::Const AstNode::bitsAsConst(int width, bool is_signed)
{ {
std::vector<RTLIL::State> bits = this->bits; std::vector<RTLIL::State> bits = this->bits;
if (width >= 0 && width < int(bits.size())) if (width >= 0 && width < GetSize(bits))
bits.resize(width); bits.resize(width);
if (width >= 0 && width > int(bits.size())) { if (width >= 0 && width > GetSize(bits)) {
RTLIL::State extbit = RTLIL::State::S0; RTLIL::State extbit = RTLIL::State::S0;
if ((is_signed || is_unsized) && !bits.empty()) if ((is_signed || is_unsized) && !bits.empty())
extbit = bits.back(); extbit = bits.back();
while (width > int(bits.size())) while (width > GetSize(bits))
bits.push_back(extbit); bits.push_back(extbit);
} }
return RTLIL::Const(bits); return RTLIL::Const(bits);
@ -1029,7 +1029,7 @@ double AstNode::asReal(bool is_signed)
val = const_neg(val, val, false, false, val.size()); val = const_neg(val, val, false, false, val.size());
double v = 0; double v = 0;
for (size_t i = 0; i < val.size(); i++) for (auto i = 0; i < val.size(); i++)
// IEEE Std 1800-2012 Par 6.12.2: Individual bits that are x or z in // IEEE Std 1800-2012 Par 6.12.2: Individual bits that are x or z in
// the net or the variable shall be treated as zero upon conversion. // the net or the variable shall be treated as zero upon conversion.
if (val.at(i) == RTLIL::State::S1) if (val.at(i) == RTLIL::State::S1)

2
frontends/ast/genrtlil.cc
View File

@ -984,7 +984,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
// unallocated enum, ignore // unallocated enum, ignore
break; break;
case AST_CONSTANT: case AST_CONSTANT:
width_hint = max(width_hint, int(bits.size())); width_hint = max(width_hint, GetSize(bits));
if (!is_signed) if (!is_signed)
sign_hint = false; sign_hint = false;
break; break;

4
frontends/ast/simplify.cc
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@ -3493,7 +3493,7 @@ skip_dynamic_range_lvalue_expansion:;
delete buf; delete buf;
uint32_t result = 0; uint32_t result = 0;
for (size_t i = 0; i < arg_value.size(); i++) for (auto i = 0; i < arg_value.size(); i++)
if (arg_value.at(i) == RTLIL::State::S1) if (arg_value.at(i) == RTLIL::State::S1)
result = i + 1; result = i + 1;
@ -4339,7 +4339,7 @@ replace_fcall_later:;
RTLIL::Const a = children[1]->bitsAsConst(width_hint, sign_hint); RTLIL::Const a = children[1]->bitsAsConst(width_hint, sign_hint);
RTLIL::Const b = children[2]->bitsAsConst(width_hint, sign_hint); RTLIL::Const b = children[2]->bitsAsConst(width_hint, sign_hint);
log_assert(a.size() == b.size()); log_assert(a.size() == b.size());
for (size_t i = 0; i < a.size(); i++) for (auto i = 0; i < a.size(); i++)
if (a[i] != b[i]) if (a[i] != b[i])
a.bits()[i] = RTLIL::State::Sx; a.bits()[i] = RTLIL::State::Sx;
newNode = mkconst_bits(a.to_bits(), sign_hint); newNode = mkconst_bits(a.to_bits(), sign_hint);

78
kernel/calc.cc
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@ -33,7 +33,7 @@ static void extend_u0(RTLIL::Const &arg, int width, bool is_signed)
if (arg.size() > 0 && is_signed) if (arg.size() > 0 && is_signed)
padding = arg.back(); padding = arg.back();
while (int(arg.size()) < width) while (GetSize(arg) < width)
arg.bits().push_back(padding); arg.bits().push_back(padding);
arg.bits().resize(width); arg.bits().resize(width);
@ -45,7 +45,7 @@ static BigInteger const2big(const RTLIL::Const &val, bool as_signed, int &undef_
BigInteger::Sign sign = BigInteger::positive; BigInteger::Sign sign = BigInteger::positive;
State inv_sign_bit = RTLIL::State::S1; State inv_sign_bit = RTLIL::State::S1;
size_t num_bits = val.size(); auto num_bits = val.size();
if (as_signed && num_bits && val[num_bits-1] == RTLIL::State::S1) { if (as_signed && num_bits && val[num_bits-1] == RTLIL::State::S1) {
inv_sign_bit = RTLIL::State::S0; inv_sign_bit = RTLIL::State::S0;
@ -53,7 +53,7 @@ static BigInteger const2big(const RTLIL::Const &val, bool as_signed, int &undef_
num_bits--; num_bits--;
} }
for (size_t i = 0; i < num_bits; i++) for (auto i = 0; i < num_bits; i++)
if (val[i] == RTLIL::State::S0 || val[i] == RTLIL::State::S1) if (val[i] == RTLIL::State::S0 || val[i] == RTLIL::State::S1)
mag.setBit(i, val[i] == inv_sign_bit); mag.setBit(i, val[i] == inv_sign_bit);
else if (undef_bit_pos < 0) else if (undef_bit_pos < 0)
@ -78,12 +78,12 @@ static RTLIL::Const big2const(const BigInteger &val, int result_len, int undef_b
if (val.getSign() < 0) if (val.getSign() < 0)
{ {
mag--; mag--;
for (int i = 0; i < result_len; i++) for (auto i = 0; i < result_len; i++)
result.bits()[i] = mag.getBit(i) ? RTLIL::State::S0 : RTLIL::State::S1; result.bits()[i] = mag.getBit(i) ? RTLIL::State::S0 : RTLIL::State::S1;
} }
else else
{ {
for (int i = 0; i < result_len; i++) for (auto i = 0; i < result_len; i++)
result.bits()[i] = mag.getBit(i) ? RTLIL::State::S1 : RTLIL::State::S0; result.bits()[i] = mag.getBit(i) ? RTLIL::State::S1 : RTLIL::State::S0;
} }
} }
@ -132,14 +132,14 @@ static RTLIL::State logic_xnor(RTLIL::State a, RTLIL::State b)
RTLIL::Const RTLIL::const_not(const RTLIL::Const &arg1, const RTLIL::Const&, bool signed1, bool, int result_len) RTLIL::Const RTLIL::const_not(const RTLIL::Const &arg1, const RTLIL::Const&, bool signed1, bool, int result_len)
{ {
if (result_len < 0) if (result_len < 0)
result_len = arg1.size(); result_len = GetSize(arg1);
RTLIL::Const arg1_ext = arg1; RTLIL::Const arg1_ext = arg1;
extend_u0(arg1_ext, result_len, signed1); extend_u0(arg1_ext, result_len, signed1);
RTLIL::Const result(RTLIL::State::Sx, result_len); RTLIL::Const result(RTLIL::State::Sx, result_len);
for (size_t i = 0; i < size_t(result_len); i++) { for (auto i = 0; i < result_len; i++) {
if (i >= arg1_ext.size()) if (i >= GetSize(arg1_ext))
result.bits()[i] = RTLIL::State::S0; result.bits()[i] = RTLIL::State::S0;
else if (arg1_ext.bits()[i] == RTLIL::State::S0) else if (arg1_ext.bits()[i] == RTLIL::State::S0)
result.bits()[i] = RTLIL::State::S1; result.bits()[i] = RTLIL::State::S1;
@ -154,15 +154,15 @@ static RTLIL::Const logic_wrapper(RTLIL::State(*logic_func)(RTLIL::State, RTLIL:
RTLIL::Const arg1, RTLIL::Const arg2, bool signed1, bool signed2, int result_len = -1) RTLIL::Const arg1, RTLIL::Const arg2, bool signed1, bool signed2, int result_len = -1)
{ {
if (result_len < 0) if (result_len < 0)
result_len = max(arg1.size(), arg2.size()); result_len = max(GetSize(arg1), GetSize(arg2));
extend_u0(arg1, result_len, signed1); extend_u0(arg1, result_len, signed1);
extend_u0(arg2, result_len, signed2); extend_u0(arg2, result_len, signed2);
RTLIL::Const result(RTLIL::State::Sx, result_len); RTLIL::Const result(RTLIL::State::Sx, result_len);
for (size_t i = 0; i < size_t(result_len); i++) { for (auto i = 0; i < result_len; i++) {
RTLIL::State a = i < arg1.size() ? arg1.bits()[i] : RTLIL::State::S0; RTLIL::State a = i < GetSize(arg1) ? arg1.bits()[i] : RTLIL::State::S0;
RTLIL::State b = i < arg2.size() ? arg2.bits()[i] : RTLIL::State::S0; RTLIL::State b = i < GetSize(arg2) ? arg2.bits()[i] : RTLIL::State::S0;
result.bits()[i] = logic_func(a, b); result.bits()[i] = logic_func(a, b);
} }
@ -193,11 +193,11 @@ static RTLIL::Const logic_reduce_wrapper(RTLIL::State initial, RTLIL::State(*log
{ {
RTLIL::State temp = initial; RTLIL::State temp = initial;
for (size_t i = 0; i < arg1.size(); i++) for (auto i = 0; i < arg1.size(); i++)
temp = logic_func(temp, arg1[i]); temp = logic_func(temp, arg1[i]);
RTLIL::Const result(temp); RTLIL::Const result(temp);
while (int(result.size()) < result_len) while (GetSize(result) < result_len)
result.bits().push_back(RTLIL::State::S0); result.bits().push_back(RTLIL::State::S0);
return result; return result;
} }
@ -240,7 +240,7 @@ RTLIL::Const RTLIL::const_logic_not(const RTLIL::Const &arg1, const RTLIL::Const
BigInteger a = const2big(arg1, signed1, undef_bit_pos_a); BigInteger a = const2big(arg1, signed1, undef_bit_pos_a);
RTLIL::Const result(a.isZero() ? undef_bit_pos_a >= 0 ? RTLIL::State::Sx : RTLIL::State::S1 : RTLIL::State::S0); RTLIL::Const result(a.isZero() ? undef_bit_pos_a >= 0 ? RTLIL::State::Sx : RTLIL::State::S1 : RTLIL::State::S0);
while (int(result.size()) < result_len) while (GetSize(result) < result_len)
result.bits().push_back(RTLIL::State::S0); result.bits().push_back(RTLIL::State::S0);
return result; return result;
} }
@ -255,7 +255,7 @@ RTLIL::Const RTLIL::const_logic_and(const RTLIL::Const &arg1, const RTLIL::Const
RTLIL::State bit_b = b.isZero() ? undef_bit_pos_b >= 0 ? RTLIL::State::Sx : RTLIL::State::S0 : RTLIL::State::S1; RTLIL::State bit_b = b.isZero() ? undef_bit_pos_b >= 0 ? RTLIL::State::Sx : RTLIL::State::S0 : RTLIL::State::S1;
RTLIL::Const result(logic_and(bit_a, bit_b)); RTLIL::Const result(logic_and(bit_a, bit_b));
while (int(result.size()) < result_len) while (GetSize(result) < result_len)
result.bits().push_back(RTLIL::State::S0); result.bits().push_back(RTLIL::State::S0);
return result; return result;
} }
@ -270,7 +270,7 @@ RTLIL::Const RTLIL::const_logic_or(const RTLIL::Const &arg1, const RTLIL::Const
RTLIL::State bit_b = b.isZero() ? undef_bit_pos_b >= 0 ? RTLIL::State::Sx : RTLIL::State::S0 : RTLIL::State::S1; RTLIL::State bit_b = b.isZero() ? undef_bit_pos_b >= 0 ? RTLIL::State::Sx : RTLIL::State::S0 : RTLIL::State::S1;
RTLIL::Const result(logic_or(bit_a, bit_b)); RTLIL::Const result(logic_or(bit_a, bit_b));
while (int(result.size()) < result_len) while (GetSize(result) < result_len)
result.bits().push_back(RTLIL::State::S0); result.bits().push_back(RTLIL::State::S0);
return result; return result;
} }
@ -286,7 +286,7 @@ static RTLIL::Const const_shift_worker(const RTLIL::Const &arg1, const RTLIL::Co
BigInteger offset = const2big(arg2, signed2, undef_bit_pos) * direction; BigInteger offset = const2big(arg2, signed2, undef_bit_pos) * direction;
if (result_len < 0) if (result_len < 0)
result_len = arg1.size(); result_len = GetSize(arg1);
RTLIL::Const result(RTLIL::State::Sx, result_len); RTLIL::Const result(RTLIL::State::Sx, result_len);
if (undef_bit_pos >= 0) if (undef_bit_pos >= 0)
@ -296,7 +296,7 @@ static RTLIL::Const const_shift_worker(const RTLIL::Const &arg1, const RTLIL::Co
BigInteger pos = BigInteger(i) + offset; BigInteger pos = BigInteger(i) + offset;
if (pos < 0) if (pos < 0)
result.bits()[i] = vacant_bits; result.bits()[i] = vacant_bits;
else if (pos >= BigInteger(int(arg1.size()))) else if (pos >= BigInteger(GetSize(arg1)))
result.bits()[i] = sign_ext ? arg1.back() : vacant_bits; result.bits()[i] = sign_ext ? arg1.back() : vacant_bits;
else else
result.bits()[i] = arg1[pos.toInt()]; result.bits()[i] = arg1[pos.toInt()];
@ -347,7 +347,7 @@ RTLIL::Const RTLIL::const_lt(const RTLIL::Const &arg1, const RTLIL::Const &arg2,
bool y = const2big(arg1, signed1, undef_bit_pos) < const2big(arg2, signed2, undef_bit_pos); bool y = const2big(arg1, signed1, undef_bit_pos) < const2big(arg2, signed2, undef_bit_pos);
RTLIL::Const result(undef_bit_pos >= 0 ? RTLIL::State::Sx : y ? RTLIL::State::S1 : RTLIL::State::S0); RTLIL::Const result(undef_bit_pos >= 0 ? RTLIL::State::Sx : y ? RTLIL::State::S1 : RTLIL::State::S0);
while (int(result.size()) < result_len) while (GetSize(result) < result_len)
result.bits().push_back(RTLIL::State::S0); result.bits().push_back(RTLIL::State::S0);
return result; return result;
} }
@ -358,7 +358,7 @@ RTLIL::Const RTLIL::const_le(const RTLIL::Const &arg1, const RTLIL::Const &arg2,
bool y = const2big(arg1, signed1, undef_bit_pos) <= const2big(arg2, signed2, undef_bit_pos); bool y = const2big(arg1, signed1, undef_bit_pos) <= const2big(arg2, signed2, undef_bit_pos);
RTLIL::Const result(undef_bit_pos >= 0 ? RTLIL::State::Sx : y ? RTLIL::State::S1 : RTLIL::State::S0); RTLIL::Const result(undef_bit_pos >= 0 ? RTLIL::State::Sx : y ? RTLIL::State::S1 : RTLIL::State::S0);
while (int(result.size()) < result_len) while (GetSize(result) < result_len)
result.bits().push_back(RTLIL::State::S0); result.bits().push_back(RTLIL::State::S0);
return result; return result;
} }
@ -369,12 +369,12 @@ RTLIL::Const RTLIL::const_eq(const RTLIL::Const &arg1, const RTLIL::Const &arg2,
RTLIL::Const arg2_ext = arg2; RTLIL::Const arg2_ext = arg2;
RTLIL::Const result(RTLIL::State::S0, result_len); RTLIL::Const result(RTLIL::State::S0, result_len);
int width = max(arg1_ext.size(), arg2_ext.size()); int width = max(GetSize(arg1_ext), GetSize(arg2_ext));
extend_u0(arg1_ext, width, signed1 && signed2); extend_u0(arg1_ext, width, signed1 && signed2);
extend_u0(arg2_ext, width, signed1 && signed2); extend_u0(arg2_ext, width, signed1 && signed2);
RTLIL::State matched_status = RTLIL::State::S1; RTLIL::State matched_status = RTLIL::State::S1;
for (size_t i = 0; i < arg1_ext.size(); i++) { for (auto i = 0; i < arg1_ext.size(); i++) {
if (arg1_ext.at(i) == RTLIL::State::S0 && arg2_ext.at(i) == RTLIL::State::S1) if (arg1_ext.at(i) == RTLIL::State::S0 && arg2_ext.at(i) == RTLIL::State::S1)
return result; return result;
if (arg1_ext.at(i) == RTLIL::State::S1 && arg2_ext.at(i) == RTLIL::State::S0) if (arg1_ext.at(i) == RTLIL::State::S1 && arg2_ext.at(i) == RTLIL::State::S0)
@ -403,11 +403,11 @@ RTLIL::Const RTLIL::const_eqx(const RTLIL::Const &arg1, const RTLIL::Const &arg2
RTLIL::Const arg2_ext = arg2; RTLIL::Const arg2_ext = arg2;
RTLIL::Const result(RTLIL::State::S0, result_len); RTLIL::Const result(RTLIL::State::S0, result_len);
int width = max(arg1_ext.size(), arg2_ext.size()); int width = max(GetSize(arg1_ext), GetSize(arg2_ext));
extend_u0(arg1_ext, width, signed1 && signed2); extend_u0(arg1_ext, width, signed1 && signed2);
extend_u0(arg2_ext, width, signed1 && signed2); extend_u0(arg2_ext, width, signed1 && signed2);
for (size_t i = 0; i < arg1_ext.size(); i++) { for (auto i = 0; i < arg1_ext.size(); i++) {
if (arg1_ext.at(i) != arg2_ext.at(i)) if (arg1_ext.at(i) != arg2_ext.at(i))
return result; return result;
} }
@ -432,7 +432,7 @@ RTLIL::Const RTLIL::const_ge(const RTLIL::Const &arg1, const RTLIL::Const &arg2,
bool y = const2big(arg1, signed1, undef_bit_pos) >= const2big(arg2, signed2, undef_bit_pos); bool y = const2big(arg1, signed1, undef_bit_pos) >= const2big(arg2, signed2, undef_bit_pos);
RTLIL::Const result(undef_bit_pos >= 0 ? RTLIL::State::Sx : y ? RTLIL::State::S1 : RTLIL::State::S0); RTLIL::Const result(undef_bit_pos >= 0 ? RTLIL::State::Sx : y ? RTLIL::State::S1 : RTLIL::State::S0);
while (int(result.size()) < result_len) while (GetSize(result) < result_len)
result.bits().push_back(RTLIL::State::S0); result.bits().push_back(RTLIL::State::S0);
return result; return result;
} }
@ -443,7 +443,7 @@ RTLIL::Const RTLIL::const_gt(const RTLIL::Const &arg1, const RTLIL::Const &arg2,
bool y = const2big(arg1, signed1, undef_bit_pos) > const2big(arg2, signed2, undef_bit_pos); bool y = const2big(arg1, signed1, undef_bit_pos) > const2big(arg2, signed2, undef_bit_pos);
RTLIL::Const result(undef_bit_pos >= 0 ? RTLIL::State::Sx : y ? RTLIL::State::S1 : RTLIL::State::S0); RTLIL::Const result(undef_bit_pos >= 0 ? RTLIL::State::Sx : y ? RTLIL::State::S1 : RTLIL::State::S0);
while (int(result.size()) < result_len) while (GetSize(result) < result_len)
result.bits().push_back(RTLIL::State::S0); result.bits().push_back(RTLIL::State::S0);
return result; return result;
} }
@ -452,21 +452,21 @@ RTLIL::Const RTLIL::const_add(const RTLIL::Const &arg1, const RTLIL::Const &arg2
{ {
int undef_bit_pos = -1; int undef_bit_pos = -1;
BigInteger y = const2big(arg1, signed1, undef_bit_pos) + const2big(arg2, signed2, undef_bit_pos); BigInteger y = const2big(arg1, signed1, undef_bit_pos) + const2big(arg2, signed2, undef_bit_pos);
return big2const(y, result_len >= 0 ? result_len : max(arg1.size(), arg2.size()), undef_bit_pos); return big2const(y, result_len >= 0 ? result_len : max(GetSize(arg1), GetSize(arg2)), undef_bit_pos);
} }
RTLIL::Const RTLIL::const_sub(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len) RTLIL::Const RTLIL::const_sub(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len)
{ {
int undef_bit_pos = -1; int undef_bit_pos = -1;
BigInteger y = const2big(arg1, signed1, undef_bit_pos) - const2big(arg2, signed2, undef_bit_pos); BigInteger y = const2big(arg1, signed1, undef_bit_pos) - const2big(arg2, signed2, undef_bit_pos);
return big2const(y, result_len >= 0 ? result_len : max(arg1.size(), arg2.size()), undef_bit_pos); return big2const(y, result_len >= 0 ? result_len : max(GetSize(arg1), GetSize(arg2)), undef_bit_pos);
} }
RTLIL::Const RTLIL::const_mul(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len) RTLIL::Const RTLIL::const_mul(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len)
{ {
int undef_bit_pos = -1; int undef_bit_pos = -1;
BigInteger y = const2big(arg1, signed1, undef_bit_pos) * const2big(arg2, signed2, undef_bit_pos); BigInteger y = const2big(arg1, signed1, undef_bit_pos) * const2big(arg2, signed2, undef_bit_pos);
return big2const(y, result_len >= 0 ? result_len : max(arg1.size(), arg2.size()), min(undef_bit_pos, 0)); return big2const(y, result_len >= 0 ? result_len : max(GetSize(arg1), GetSize(arg2)), min(undef_bit_pos, 0));
} }
// truncating division // truncating division
@ -480,7 +480,7 @@ RTLIL::Const RTLIL::const_div(const RTLIL::Const &arg1, const RTLIL::Const &arg2
bool result_neg = (a.getSign() == BigInteger::negative) != (b.getSign() == BigInteger::negative); bool result_neg = (a.getSign() == BigInteger::negative) != (b.getSign() == BigInteger::negative);
a = a.getSign() == BigInteger::negative ? -a : a; a = a.getSign() == BigInteger::negative ? -a : a;
b = b.getSign() == BigInteger::negative ? -b : b; b = b.getSign() == BigInteger::negative ? -b : b;
return big2const(result_neg ? -(a / b) : (a / b), result_len >= 0 ? result_len : max(arg1.size(), arg2.size()), min(undef_bit_pos, 0)); return big2const(result_neg ? -(a / b) : (a / b), result_len >= 0 ? result_len : max(GetSize(arg1), GetSize(arg2)), min(undef_bit_pos, 0));
} }
// truncating modulo // truncating modulo
@ -494,7 +494,7 @@ RTLIL::Const RTLIL::const_mod(const RTLIL::Const &arg1, const RTLIL::Const &arg2
bool result_neg = a.getSign() == BigInteger::negative; bool result_neg = a.getSign() == BigInteger::negative;
a = a.getSign() == BigInteger::negative ? -a : a; a = a.getSign() == BigInteger::negative ? -a : a;
b = b.getSign() == BigInteger::negative ? -b : b; b = b.getSign() == BigInteger::negative ? -b : b;
return big2const(result_neg ? -(a % b) : (a % b), result_len >= 0 ? result_len : max(arg1.size(), arg2.size()), min(undef_bit_pos, 0)); return big2const(result_neg ? -(a % b) : (a % b), result_len >= 0 ? result_len : max(GetSize(arg1), GetSize(arg2)), min(undef_bit_pos, 0));
} }
RTLIL::Const RTLIL::const_divfloor(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len) RTLIL::Const RTLIL::const_divfloor(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len)
@ -516,7 +516,7 @@ RTLIL::Const RTLIL::const_divfloor(const RTLIL::Const &arg1, const RTLIL::Const
// bigint division with negative numbers is wonky, make sure we only negate at the very end // bigint division with negative numbers is wonky, make sure we only negate at the very end
result = -((a + b - 1) / b); result = -((a + b - 1) / b);
} }
return big2const(result, result_len >= 0 ? result_len : max(arg1.size(), arg2.size()), min(undef_bit_pos, 0)); return big2const(result, result_len >= 0 ? result_len : max(GetSize(arg1), GetSize(arg2)), min(undef_bit_pos, 0));
} }
RTLIL::Const RTLIL::const_modfloor(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len) RTLIL::Const RTLIL::const_modfloor(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len)
@ -539,7 +539,7 @@ RTLIL::Const RTLIL::const_modfloor(const RTLIL::Const &arg1, const RTLIL::Const
} else { } else {
modulo = b_sign == BigInteger::negative ? truncated - b : truncated + b; modulo = b_sign == BigInteger::negative ? truncated - b : truncated + b;
} }
return big2const(modulo, result_len >= 0 ? result_len : max(arg1.size(), arg2.size()), min(undef_bit_pos, 0)); return big2const(modulo, result_len >= 0 ? result_len : max(GetSize(arg1), GetSize(arg2)), min(undef_bit_pos, 0));
} }
RTLIL::Const RTLIL::const_pow(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len) RTLIL::Const RTLIL::const_pow(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len)
@ -590,7 +590,7 @@ RTLIL::Const RTLIL::const_pow(const RTLIL::Const &arg1, const RTLIL::Const &arg2
y *= -1; y *= -1;
} }
return big2const(y, result_len >= 0 ? result_len : max(arg1.size(), arg2.size()), min(undef_bit_pos, 0)); return big2const(y, result_len >= 0 ? result_len : max(GetSize(arg1), GetSize(arg2)), min(undef_bit_pos, 0));
} }
RTLIL::Const RTLIL::const_pos(const RTLIL::Const &arg1, const RTLIL::Const&, bool signed1, bool, int result_len) RTLIL::Const RTLIL::const_pos(const RTLIL::Const &arg1, const RTLIL::Const&, bool signed1, bool, int result_len)
@ -626,7 +626,7 @@ RTLIL::Const RTLIL::const_mux(const RTLIL::Const &arg1, const RTLIL::Const &arg2
return arg2; return arg2;
RTLIL::Const ret = arg1; RTLIL::Const ret = arg1;
for (int i = 0; i < ret.size(); i++) for (auto i = 0; i < ret.size(); i++)
if (ret[i] != arg2[i]) if (ret[i] != arg2[i])
ret.bits()[i] = State::Sx; ret.bits()[i] = State::Sx;
return ret; return ret;
@ -640,7 +640,7 @@ RTLIL::Const RTLIL::const_pmux(const RTLIL::Const &arg1, const RTLIL::Const &arg
if (!arg3.is_onehot()) if (!arg3.is_onehot())
return RTLIL::Const(State::Sx, arg1.size()); return RTLIL::Const(State::Sx, arg1.size());
for (int i = 0; i < arg3.size(); i++) for (auto i = 0; i < arg3.size(); i++)
if (arg3[i] == State::S1) if (arg3[i] == State::S1)
return RTLIL::Const(std::vector<RTLIL::State>(arg2.begin() + i*arg1.size(), arg2.begin() + (i+1)*arg1.size())); return RTLIL::Const(std::vector<RTLIL::State>(arg2.begin() + i*arg1.size(), arg2.begin() + (i+1)*arg1.size()));
@ -702,7 +702,7 @@ RTLIL::Const RTLIL::const_bweqx(const RTLIL::Const &arg1, const RTLIL::Const &ar
{ {
log_assert(arg2.size() == arg1.size()); log_assert(arg2.size() == arg1.size());
RTLIL::Const result(RTLIL::State::S0, arg1.size()); RTLIL::Const result(RTLIL::State::S0, arg1.size());
for (int i = 0; i < arg1.size(); i++) for (auto i = 0; i < arg1.size(); i++)
result.bits()[i] = arg1[i] == arg2[i] ? State::S1 : State::S0; result.bits()[i] = arg1[i] == arg2[i] ? State::S1 : State::S0;
return result; return result;
@ -713,7 +713,7 @@ RTLIL::Const RTLIL::const_bwmux(const RTLIL::Const &arg1, const RTLIL::Const &ar
log_assert(arg2.size() == arg1.size()); log_assert(arg2.size() == arg1.size());
log_assert(arg3.size() == arg1.size()); log_assert(arg3.size() == arg1.size());
RTLIL::Const result(RTLIL::State::Sx, arg1.size()); RTLIL::Const result(RTLIL::State::Sx, arg1.size());
for (int i = 0; i < arg1.size(); i++) { for (auto i = 0; i < arg1.size(); i++) {
if (arg3[i] != State::Sx || arg1[i] == arg2[i]) if (arg3[i] != State::Sx || arg1[i] == arg2[i])
result.bits()[i] = arg3[i] == State::S1 ? arg2[i] : arg1[i]; result.bits()[i] = arg3[i] == State::S1 ? arg2[i] : arg1[i];
} }

12
kernel/rtlil.cc
View File

@ -380,7 +380,7 @@ int RTLIL::Const::as_int(bool is_signed) const
return ret; return ret;
} }
size_t RTLIL::Const::get_min_size(bool is_signed) const int RTLIL::Const::get_min_size(bool is_signed) const
{ {
if (empty()) return 0; if (empty()) return 0;
@ -391,7 +391,7 @@ size_t RTLIL::Const::get_min_size(bool is_signed) const
else else
leading_bit = RTLIL::State::S0; leading_bit = RTLIL::State::S0;
size_t idx = size(); auto idx = size();
while (idx > 0 && (*this)[idx -1] == leading_bit) { while (idx > 0 && (*this)[idx -1] == leading_bit) {
idx--; idx--;
} }
@ -406,22 +406,22 @@ size_t RTLIL::Const::get_min_size(bool is_signed) const
void RTLIL::Const::compress(bool is_signed) void RTLIL::Const::compress(bool is_signed)
{ {
size_t idx = get_min_size(is_signed); auto idx = get_min_size(is_signed);
bits().erase(bits().begin() + idx, bits().end()); bits().erase(bits().begin() + idx, bits().end());
} }
std::optional<int> RTLIL::Const::as_int_compress(bool is_signed) const std::optional<int> RTLIL::Const::as_int_compress(bool is_signed) const
{ {
size_t size = get_min_size(is_signed); auto size = get_min_size(is_signed);
if(size == 0 || size > 32) if(size == 0 || size > 32)
return std::nullopt; return std::nullopt;
int32_t ret = 0; int32_t ret = 0;
for (size_t i = 0; i < size && i < 32; i++) for (auto i = 0; i < size && i < 32; i++)
if ((*this)[i] == State::S1) if ((*this)[i] == State::S1)
ret |= 1 << i; ret |= 1 << i;
if (is_signed && (*this)[size-1] == State::S1) if (is_signed && (*this)[size-1] == State::S1)
for (size_t i = size; i < 32; i++) for (auto i = size; i < 32; i++)
ret |= 1 << i; ret |= 1 << i;
return ret; return ret;
} }

2
kernel/rtlil.h
View File

@ -780,7 +780,7 @@ public:
RTLIL::Const extract(int offset, int len = 1, RTLIL::State padding = RTLIL::State::S0) const; RTLIL::Const extract(int offset, int len = 1, RTLIL::State padding = RTLIL::State::S0) const;
// find the MSB without redundant leading bits // find the MSB without redundant leading bits
size_t get_min_size(bool is_signed) const; int get_min_size(bool is_signed) const;
// compress representation to the minimum required bits // compress representation to the minimum required bits
void compress(bool is_signed = false); void compress(bool is_signed = false);

6
passes/fsm/fsm_map.cc
View File

@ -54,7 +54,7 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const
RTLIL::Const pattern = it.first; RTLIL::Const pattern = it.first;
RTLIL::SigSpec eq_sig_a, eq_sig_b, or_sig; RTLIL::SigSpec eq_sig_a, eq_sig_b, or_sig;
for (size_t j = 0; j < pattern.size(); j++) for (auto j = 0; j < pattern.size(); j++)
if (pattern[j] == RTLIL::State::S0 || pattern[j] == RTLIL::State::S1) { if (pattern[j] == RTLIL::State::S0 || pattern[j] == RTLIL::State::S1) {
eq_sig_a.append(ctrl_in.extract(j, 1)); eq_sig_a.append(ctrl_in.extract(j, 1));
eq_sig_b.append(RTLIL::SigSpec(pattern[j])); eq_sig_b.append(RTLIL::SigSpec(pattern[j]));
@ -198,7 +198,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
RTLIL::Const state = fsm_data.state_table[i]; RTLIL::Const state = fsm_data.state_table[i];
RTLIL::SigSpec sig_a, sig_b; RTLIL::SigSpec sig_a, sig_b;
for (size_t j = 0; j < state.size(); j++) for (auto j = 0; j < state.size(); j++)
if (state[j] == RTLIL::State::S0 || state[j] == RTLIL::State::S1) { if (state[j] == RTLIL::State::S0 || state[j] == RTLIL::State::S1) {
sig_a.append(RTLIL::SigSpec(state_wire, j)); sig_a.append(RTLIL::SigSpec(state_wire, j));
sig_b.append(RTLIL::SigSpec(state[j])); sig_b.append(RTLIL::SigSpec(state[j]));
@ -261,7 +261,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
for (size_t i = 0; i < fsm_data.state_table.size(); i++) { for (size_t i = 0; i < fsm_data.state_table.size(); i++) {
RTLIL::Const state = fsm_data.state_table[i]; RTLIL::Const state = fsm_data.state_table[i];
int bit_idx = -1; int bit_idx = -1;
for (size_t j = 0; j < state.size(); j++) for (auto j = 0; j < state.size(); j++)
if (state[j] == RTLIL::State::S1) if (state[j] == RTLIL::State::S1)
bit_idx = j; bit_idx = j;
if (bit_idx >= 0) if (bit_idx >= 0)

2
techlibs/quicklogic/ql_dsp_simd.cc
View File

@ -60,7 +60,7 @@ struct QlDspSimdPass : public Pass {
// .......................................... // ..........................................
const size_t m_ModeBitsSize = 80; const int m_ModeBitsSize = 80;
// DSP parameters // DSP parameters
const std::vector<std::string> m_DspParams = {"COEFF_3", "COEFF_2", "COEFF_1", "COEFF_0"}; const std::vector<std::string> m_DspParams = {"COEFF_3", "COEFF_2", "COEFF_1", "COEFF_0"};