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Remove SRL16/32 from cells_xtra

This commit is contained in:
Eddie Hung 2019-02-28 13:56:45 -08:00
parent 73ddab6960
commit 1da0909662
2 changed files with 2 additions and 18 deletions
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4
techlibs/xilinx/cells_xtra.sh
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@ -134,8 +134,8 @@ function xtract_cell_decl()
xtract_cell_decl ROM256X1 xtract_cell_decl ROM256X1
xtract_cell_decl ROM32X1 xtract_cell_decl ROM32X1
xtract_cell_decl ROM64X1 xtract_cell_decl ROM64X1
xtract_cell_decl SRL16E #xtract_cell_decl SRL16E
xtract_cell_decl SRLC32E #xtract_cell_decl SRLC32E
xtract_cell_decl STARTUPE2 xtract_cell_decl STARTUPE2
xtract_cell_decl USR_ACCESSE2 xtract_cell_decl USR_ACCESSE2
xtract_cell_decl XADC xtract_cell_decl XADC

16
techlibs/xilinx/cells_xtra.v
View File

@ -3824,22 +3824,6 @@ module ROM64X1 (...);
input A0, A1, A2, A3, A4, A5; input A0, A1, A2, A3, A4, A5;
endmodule endmodule
module SRL16E (...);
parameter [15:0] INIT = 16'h0000;
parameter [0:0] IS_CLK_INVERTED = 1'b0;
output Q;
input A0, A1, A2, A3, CE, CLK, D;
endmodule
module SRLC32E (...);
parameter [31:0] INIT = 32'h00000000;
parameter [0:0] IS_CLK_INVERTED = 1'b0;
output Q;
output Q31;
input [4:0] A;
input CE, CLK, D;
endmodule
module STARTUPE2 (...); module STARTUPE2 (...);
parameter PROG_USR = "FALSE"; parameter PROG_USR = "FALSE";
parameter real SIM_CCLK_FREQ = 0.0; parameter real SIM_CCLK_FREQ = 0.0;