mirror of https://github.com/YosysHQ/yosys.git
Bugfixes in handling of "keep" attribute on wires
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5dd3e93e8f
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@ -136,7 +136,7 @@ struct OptMuxtreeWorker
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}
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}
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}
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}
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for (auto wire : module->wires()) {
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for (auto wire : module->wires()) {
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if (wire->port_output)
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if (wire->port_output || wire->get_bool_attribute("\\keep"))
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for (int idx : sig2bits(RTLIL::SigSpec(wire)))
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for (int idx : sig2bits(RTLIL::SigSpec(wire)))
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bit2info[idx].seen_non_mux = true;
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bit2info[idx].seen_non_mux = true;
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}
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}
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@ -51,6 +51,7 @@ struct WreduceWorker
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std::set<Cell*, IdString::compare_ptr_by_name<Cell>> work_queue_cells;
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std::set<Cell*, IdString::compare_ptr_by_name<Cell>> work_queue_cells;
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std::set<SigBit> work_queue_bits;
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std::set<SigBit> work_queue_bits;
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pool<SigBit> keep_bits;
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WreduceWorker(WreduceConfig *config, Module *module) :
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WreduceWorker(WreduceConfig *config, Module *module) :
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config(config), module(module), mi(module) { }
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config(config), module(module), mi(module) { }
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@ -68,7 +69,7 @@ struct WreduceWorker
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for (int i = GetSize(sig_y)-1; i >= 0; i--)
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for (int i = GetSize(sig_y)-1; i >= 0; i--)
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{
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{
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auto info = mi.query(sig_y[i]);
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auto info = mi.query(sig_y[i]);
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if (!info->is_output && GetSize(info->ports) <= 1) {
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if (!info->is_output && GetSize(info->ports) <= 1 && !keep_bits.count(mi.sigmap(sig_y[i]))) {
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bits_removed.push_back(Sx);
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bits_removed.push_back(Sx);
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continue;
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continue;
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}
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}
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@ -265,6 +266,11 @@ struct WreduceWorker
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void run()
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void run()
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{
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{
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for (auto w : module->wires())
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if (w->get_bool_attribute("\\keep"))
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for (auto bit : mi.sigmap(w))
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keep_bits.insert(bit);
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for (auto c : module->selected_cells())
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for (auto c : module->selected_cells())
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work_queue_cells.insert(c);
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work_queue_cells.insert(c);
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