mirror of https://github.com/YosysHQ/yosys.git
abc9_ops -prep_dff: insert async s/r mux in holes when replacing $_DFF_*
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@ -106,14 +106,23 @@ void prep_dff(RTLIL::Module *module)
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SigMap sigmap(holes_module);
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dict<SigSpec, SigSpec> replace;
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for (auto it = holes_module->cells_.begin(); it != holes_module->cells_.end(); ) {
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auto cell = it->second;
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if (cell->type.in("$_DFF_N_", "$_DFF_NN0_", "$_DFF_NN1_", "$_DFF_NP0_", "$_DFF_NP1_",
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"$_DFF_P_", "$_DFF_PN0_", "$_DFF_PN1", "$_DFF_PP0_", "$_DFF_PP1_")) {
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for (auto cell : holes_module->cells().to_vector()) {
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if (!cell->type.in("$_DFF_N_", "$_DFF_NN0_", "$_DFF_NN1_", "$_DFF_NP0_", "$_DFF_NP1_",
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"$_DFF_P_", "$_DFF_PN0_", "$_DFF_PN1", "$_DFF_PP0_", "$_DFF_PP1_"))
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continue;
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SigBit D = cell->getPort("\\D");
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SigBit Q = cell->getPort("\\Q");
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// Emulate async control embedded inside $_DFF_* cell with mux in front of D
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if (cell->type.in("$_DFF_NN0_", "$_DFF_PN0_"))
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D = holes_module->MuxGate(NEW_ID, State::S0, D, cell->getPort("\\R"));
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else if (cell->type.in("$_DFF_NN1_", "$_DFF_PN1_"))
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D = holes_module->MuxGate(NEW_ID, State::S1, D, cell->getPort("\\R"));
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else if (cell->type.in("$_DFF_NP0_", "$_DFF_PP0_"))
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D = holes_module->MuxGate(NEW_ID, D, State::S0, cell->getPort("\\R"));
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else if (cell->type.in("$_DFF_NP1_", "$_DFF_PP1_"))
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D = holes_module->MuxGate(NEW_ID, D, State::S1, cell->getPort("\\R"));
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// Remove the $_DFF_* cell from what needs to be a combinatorial box
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it = holes_module->cells_.erase(it);
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holes_module->remove(cell);
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Wire *port;
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if (GetSize(Q.wire) == 1)
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port = holes_module->wire(stringf("$abc%s", Q.wire->name.c_str()));
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@ -136,9 +145,6 @@ void prep_dff(RTLIL::Module *module)
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log_assert(currQ);
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holes_module->connect(Q, currQ);
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}
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else
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++it;
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}
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for (auto &conn : holes_module->connections_)
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conn.second = replace.at(sigmap(conn.second), conn.second);
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