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abc9_ops -prep_dff: insert async s/r mux in holes when replacing $_DFF_*

This commit is contained in:
Eddie Hung 2020-01-23 14:58:56 -08:00
parent af0e7637a2
commit 1d4314d888
1 changed files with 37 additions and 31 deletions
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22
passes/techmap/abc9_ops.cc
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@ -106,14 +106,23 @@ void prep_dff(RTLIL::Module *module)
SigMap sigmap(holes_module); SigMap sigmap(holes_module);
dict<SigSpec, SigSpec> replace; dict<SigSpec, SigSpec> replace;
for (auto it = holes_module->cells_.begin(); it != holes_module->cells_.end(); ) { for (auto cell : holes_module->cells().to_vector()) {
auto cell = it->second; if (!cell->type.in("$_DFF_N_", "$_DFF_NN0_", "$_DFF_NN1_", "$_DFF_NP0_", "$_DFF_NP1_",
if (cell->type.in("$_DFF_N_", "$_DFF_NN0_", "$_DFF_NN1_", "$_DFF_NP0_", "$_DFF_NP1_", "$_DFF_P_", "$_DFF_PN0_", "$_DFF_PN1", "$_DFF_PP0_", "$_DFF_PP1_"))
"$_DFF_P_", "$_DFF_PN0_", "$_DFF_PN1", "$_DFF_PP0_", "$_DFF_PP1_")) { continue;
SigBit D = cell->getPort("\\D"); SigBit D = cell->getPort("\\D");
SigBit Q = cell->getPort("\\Q"); SigBit Q = cell->getPort("\\Q");
// Emulate async control embedded inside $_DFF_* cell with mux in front of D
if (cell->type.in("$_DFF_NN0_", "$_DFF_PN0_"))
D = holes_module->MuxGate(NEW_ID, State::S0, D, cell->getPort("\\R"));
else if (cell->type.in("$_DFF_NN1_", "$_DFF_PN1_"))
D = holes_module->MuxGate(NEW_ID, State::S1, D, cell->getPort("\\R"));
else if (cell->type.in("$_DFF_NP0_", "$_DFF_PP0_"))
D = holes_module->MuxGate(NEW_ID, D, State::S0, cell->getPort("\\R"));
else if (cell->type.in("$_DFF_NP1_", "$_DFF_PP1_"))
D = holes_module->MuxGate(NEW_ID, D, State::S1, cell->getPort("\\R"));
// Remove the $_DFF_* cell from what needs to be a combinatorial box // Remove the $_DFF_* cell from what needs to be a combinatorial box
it = holes_module->cells_.erase(it); holes_module->remove(cell);
Wire *port; Wire *port;
if (GetSize(Q.wire) == 1) if (GetSize(Q.wire) == 1)
port = holes_module->wire(stringf("$abc%s", Q.wire->name.c_str())); port = holes_module->wire(stringf("$abc%s", Q.wire->name.c_str()));
@ -136,9 +145,6 @@ void prep_dff(RTLIL::Module *module)
log_assert(currQ); log_assert(currQ);
holes_module->connect(Q, currQ); holes_module->connect(Q, currQ);
} }
else
++it;
}
for (auto &conn : holes_module->connections_) for (auto &conn : holes_module->connections_)
conn.second = replace.at(sigmap(conn.second), conn.second); conn.second = replace.at(sigmap(conn.second), conn.second);