mirror of https://github.com/YosysHQ/yosys.git
aiger2: Use `REDUCE` for reduction ops
This commit is contained in:
parent
6c1fa45995
commit
1cfb9023c4
|
@ -262,21 +262,21 @@ struct Index {
|
||||||
} else if (cell->type.in(REDUCE_OPS, ID($logic_not))) {
|
} else if (cell->type.in(REDUCE_OPS, ID($logic_not))) {
|
||||||
SigSpec inport = cell->getPort(ID::A);
|
SigSpec inport = cell->getPort(ID::A);
|
||||||
|
|
||||||
log_assert(inport.size() > 0); // TODO
|
std::vector<Lit> lits;
|
||||||
|
for (int i = 0; i < inport.size(); i++) {
|
||||||
Lit acc = visit(cursor, inport[0]);
|
Lit lit = visit(cursor, inport[i]);
|
||||||
for (int i = 1; i < inport.size(); i++) {
|
if (cell->type.in(ID($reduce_and), ID($reduce_xor), ID($reduce_xnor))) {
|
||||||
Lit l = visit(cursor, inport[i]);
|
lits.push_back(lit);
|
||||||
if (cell->type == ID($reduce_and)) {
|
|
||||||
acc = AND(acc, l);
|
|
||||||
} else if (cell->type.in(ID($reduce_or), ID($reduce_bool), ID($logic_not))) {
|
} else if (cell->type.in(ID($reduce_or), ID($reduce_bool), ID($logic_not))) {
|
||||||
acc = OR(acc, l);
|
lits.push_back(NOT(lit));
|
||||||
} else if (cell->type.in(ID($reduce_xor), ID($reduce_xnor))) {
|
} else {
|
||||||
acc = XOR(acc, l);
|
log_abort();
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
if (!cell->type.in(ID($reduce_xnor), ID($logic_not)))
|
Lit acc = REDUCE(lits, cell->type.in(ID($reduce_xor), ID($reduce_xnor)));
|
||||||
|
|
||||||
|
if (!cell->type.in(ID($reduce_xnor), ID($reduce_or), ID($reduce_bool)))
|
||||||
return acc;
|
return acc;
|
||||||
else
|
else
|
||||||
return NOT(acc);
|
return NOT(acc);
|
||||||
|
|
Loading…
Reference in New Issue