mirror of https://github.com/YosysHQ/yosys.git
aiger2: Use `REDUCE` for reduction ops
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6c1fa45995
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@ -262,21 +262,21 @@ struct Index {
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} else if (cell->type.in(REDUCE_OPS, ID($logic_not))) {
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SigSpec inport = cell->getPort(ID::A);
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log_assert(inport.size() > 0); // TODO
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Lit acc = visit(cursor, inport[0]);
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for (int i = 1; i < inport.size(); i++) {
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Lit l = visit(cursor, inport[i]);
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if (cell->type == ID($reduce_and)) {
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acc = AND(acc, l);
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std::vector<Lit> lits;
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for (int i = 0; i < inport.size(); i++) {
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Lit lit = visit(cursor, inport[i]);
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if (cell->type.in(ID($reduce_and), ID($reduce_xor), ID($reduce_xnor))) {
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lits.push_back(lit);
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} else if (cell->type.in(ID($reduce_or), ID($reduce_bool), ID($logic_not))) {
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acc = OR(acc, l);
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} else if (cell->type.in(ID($reduce_xor), ID($reduce_xnor))) {
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acc = XOR(acc, l);
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lits.push_back(NOT(lit));
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} else {
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log_abort();
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}
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}
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if (!cell->type.in(ID($reduce_xnor), ID($logic_not)))
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Lit acc = REDUCE(lits, cell->type.in(ID($reduce_xor), ID($reduce_xnor)));
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if (!cell->type.in(ID($reduce_xnor), ID($reduce_or), ID($reduce_bool)))
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return acc;
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else
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return NOT(acc);
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