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verific: allow memories to be inferred in loops (vhdl)

This commit is contained in:
Miodrag Milanovic 2022-04-18 09:10:28 +02:00
parent d23260d381
commit 1cc281ca6f
1 changed files with 1 additions and 0 deletions
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frontends/verific/verific.cc
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@ -2553,6 +2553,7 @@ struct VerificPass : public Pass {
#ifdef VERIFIC_VHDL_SUPPORT #ifdef VERIFIC_VHDL_SUPPORT
RuntimeFlags::SetVar("vhdl_extract_dualport_rams", 0); RuntimeFlags::SetVar("vhdl_extract_dualport_rams", 0);
RuntimeFlags::SetVar("vhdl_extract_multiport_rams", 1); RuntimeFlags::SetVar("vhdl_extract_multiport_rams", 1);
RuntimeFlags::SetVar("vhdl_allow_any_ram_in_loop", 1);
RuntimeFlags::SetVar("vhdl_support_variable_slice", 1); RuntimeFlags::SetVar("vhdl_support_variable_slice", 1);
RuntimeFlags::SetVar("vhdl_ignore_assertion_statements", 0); RuntimeFlags::SetVar("vhdl_ignore_assertion_statements", 0);