diff --git a/frontends/liberty/liberty.cc b/frontends/liberty/liberty.cc index e183cbf10..91d390131 100644 --- a/frontends/liberty/liberty.cc +++ b/frontends/liberty/liberty.cc @@ -462,6 +462,9 @@ struct LibertyFrontend : public Frontend { log(" -ignore_miss_data_latch\n"); log(" ignore latches with missing data and/or enable pins\n"); log("\n"); + log(" -ignore_buses\n"); + log(" ignore cells with bus interfaces (wide ports)\n"); + log("\n"); log(" -setattr \n"); log(" set the specified attribute (to the value 1) on all loaded modules\n"); log("\n"); @@ -478,6 +481,7 @@ struct LibertyFrontend : public Frontend { bool flag_ignore_miss_func = false; bool flag_ignore_miss_dir = false; bool flag_ignore_miss_data_latch = false; + bool flag_ignore_buses = false; bool flag_unit_delay = false; std::vector attributes; @@ -514,6 +518,10 @@ struct LibertyFrontend : public Frontend { flag_ignore_miss_data_latch = true; continue; } + if (arg == "-ignore_buses") { + flag_ignore_buses = true; + continue; + } if (arg == "-setattr" && argidx+1 < args.size()) { attributes.push_back(RTLIL::escape_id(args[++argidx])); continue; @@ -542,27 +550,13 @@ struct LibertyFrontend : public Frontend { if (cell->id != "cell" || cell->args.size() != 1) continue; - std::string cell_name = RTLIL::escape_id(cell->args.at(0)); - - if (design->has(cell_name)) { - Module *existing_mod = design->module(cell_name); - if (!flag_nooverwrite && !flag_overwrite && !existing_mod->get_bool_attribute(ID::blackbox)) { - log_error("Re-definition of cell/module %s!\n", log_id(cell_name)); - } else if (flag_nooverwrite) { - log("Ignoring re-definition of module %s.\n", log_id(cell_name)); - continue; - } else { - log("Replacing existing%s module %s.\n", existing_mod->get_bool_attribute(ID::blackbox) ? " blackbox" : "", log_id(cell_name)); - design->remove(existing_mod); - } - } - // log("Processing cell type %s.\n", RTLIL::unescape_id(cell_name).c_str()); std::map> type_map = global_type_map; parse_type_map(type_map, cell); RTLIL::Module *module = new RTLIL::Module; + std::string cell_name = RTLIL::escape_id(cell->args.at(0)); module->name = cell_name; if (flag_lib) @@ -571,6 +565,10 @@ struct LibertyFrontend : public Frontend { if (flag_wb) module->set_bool_attribute(ID::whitebox); + const LibertyAst *area = cell->find("area"); + if (area) + module->attributes[ID::area] = area->value; + for (auto &attr : attributes) module->attributes[attr] = 1; @@ -595,6 +593,12 @@ struct LibertyFrontend : public Frontend { if (node->id == "bus" && node->args.size() == 1) { + if (flag_ignore_buses) { + log("Ignoring cell %s with a bus interface %s.\n", log_id(module->name), node->args.at(0).c_str()); + delete module; + goto skip_cell; + } + if (!flag_lib) log_error("Error in cell %s: bus interfaces are only supported in -lib mode.\n", log_id(cell_name)); @@ -662,6 +666,10 @@ struct LibertyFrontend : public Frontend { RTLIL::Wire *wire = module->wires_.at(RTLIL::escape_id(node->args.at(0))); log_assert(wire); + const LibertyAst *capacitance = node->find("capacitance"); + if (capacitance) + wire->attributes[ID::capacitance] = capacitance->value; + if (dir && dir->value == "inout") { wire->port_input = true; wire->port_output = true; @@ -739,6 +747,20 @@ struct LibertyFrontend : public Frontend { } } + if (design->has(cell_name)) { + Module *existing_mod = design->module(cell_name); + if (!flag_nooverwrite && !flag_overwrite && !existing_mod->get_bool_attribute(ID::blackbox)) { + log_error("Re-definition of cell/module %s!\n", log_id(cell_name)); + } else if (flag_nooverwrite) { + log("Ignoring re-definition of module %s.\n", log_id(cell_name)); + delete module; + goto skip_cell; + } else { + log("Replacing existing%s module %s.\n", existing_mod->get_bool_attribute(ID::blackbox) ? " blackbox" : "", log_id(cell_name)); + design->remove(existing_mod); + } + } + module->fixup_ports(); design->add(module); cell_count++; diff --git a/kernel/constids.inc b/kernel/constids.inc index d1bbb8eda..d68e2dfe6 100644 --- a/kernel/constids.inc +++ b/kernel/constids.inc @@ -274,3 +274,5 @@ X(X) X(xprop_decoder) X(Y) X(Y_WIDTH) +X(area) +X(capacitance) diff --git a/tests/liberty/.gitignore b/tests/liberty/.gitignore index 8763aaac5..2ee56e9d1 100644 --- a/tests/liberty/.gitignore +++ b/tests/liberty/.gitignore @@ -1,3 +1,3 @@ *.log -*.filtered +/*.filtered *.verilogsim diff --git a/tests/liberty/foundry_data/.gitignore b/tests/liberty/foundry_data/.gitignore new file mode 100644 index 000000000..3b97f2a3e --- /dev/null +++ b/tests/liberty/foundry_data/.gitignore @@ -0,0 +1,2 @@ +*.lib +*.lib.filtered diff --git a/tests/liberty/foundry_data/RM_IHPSG13_1P_64x64_c2_bm_bist_typ_1p20V_25C.lib.filtered.gz b/tests/liberty/foundry_data/RM_IHPSG13_1P_64x64_c2_bm_bist_typ_1p20V_25C.lib.filtered.gz new file mode 100644 index 000000000..826d77060 Binary files /dev/null and b/tests/liberty/foundry_data/RM_IHPSG13_1P_64x64_c2_bm_bist_typ_1p20V_25C.lib.filtered.gz differ diff --git a/tests/liberty/foundry_data/rules.txt b/tests/liberty/foundry_data/rules.txt new file mode 100644 index 000000000..1e739f552 --- /dev/null +++ b/tests/liberty/foundry_data/rules.txt @@ -0,0 +1,16 @@ +-wire_load +-wire_load_selection +-default_wire_load +-default_wire_load_area +-default_wire_load_capacitance +-default_wire_load_mode +-default_wire_load_resistance +-default_cell_leakage_power +-default_wire_load_selection +-default_leakage_power_density +-lu_table_template +-power_lut_template +-leakage_power +-cell_leakage_power +-leakage_power +-internal_power diff --git a/tests/liberty/foundry_data/sg13g2_stdcell_typ_1p20V_25C.lib.filtered.gz b/tests/liberty/foundry_data/sg13g2_stdcell_typ_1p20V_25C.lib.filtered.gz new file mode 100644 index 000000000..81c100e43 Binary files /dev/null and b/tests/liberty/foundry_data/sg13g2_stdcell_typ_1p20V_25C.lib.filtered.gz differ diff --git a/tests/liberty/options_test.ys b/tests/liberty/options_test.ys new file mode 100644 index 000000000..54957950e --- /dev/null +++ b/tests/liberty/options_test.ys @@ -0,0 +1,23 @@ +# Test memory macro gets ignored due to -ignore_buses +read_verilog -noblackbox <Y arc on nand2_1 exists +select -assert-any =sg13g2_nand2_1/i:A %co1:+$specify2[SRC] =sg13g2_nand2_1/o:Y %co1:+$specify2[DST] %i + +# D->Q arc on sdfbbp_1 doesn't +select -assert-none =sg13g2_sdfbbp_1/i:D %co1:+$specify2[SRC] =sg13g2_nand2_1/o:Q %co1:+$specify2[DST] %i diff --git a/tests/liberty/unit_delay.ys b/tests/liberty/unit_delay.ys deleted file mode 100644 index 8dd409183..000000000 --- a/tests/liberty/unit_delay.ys +++ /dev/null @@ -1,3 +0,0 @@ -# Nothing gets imported: the file lacks timing data -read_liberty -wb -unit_delay normal.lib -select -assert-none =*/t:$specify*