mirror of https://github.com/YosysHQ/yosys.git
Added mux support to wreduce command
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parent
91dd87e60b
commit
1c182cedb7
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@ -28,48 +28,23 @@ using namespace RTLIL;
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PRIVATE_NAMESPACE_BEGIN
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PRIVATE_NAMESPACE_BEGIN
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static inline std::set<IdString> &operator<<(std::set<IdString> &set, IdString id) {
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set.insert(id);
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return set;
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}
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struct WreduceConfig
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struct WreduceConfig
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{
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{
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std::set<IdString> supported_cell_types;
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std::set<IdString> supported_cell_types;
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WreduceConfig()
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WreduceConfig()
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{
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{
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supported_cell_types.insert("$not");
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supported_cell_types << "$not" << "$pos" << "$bu0" << "$neg";
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supported_cell_types.insert("$pos");
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supported_cell_types << "$and" << "$or" << "$xor" << "$xnor";
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supported_cell_types.insert("$bu0");
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supported_cell_types << "$shl" << "$shr" << "$sshl" << "$sshr" << "$shift" << "$shiftx";
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supported_cell_types.insert("$neg");
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supported_cell_types << "$lt" << "$le" << "$eq" << "$ne" << "$eqx" << "$nex" << "$ge" << "$gt";
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supported_cell_types << "$add" << "$sub"; // << "$mul" << "$div" << "$mod" << "$pow"
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supported_cell_types.insert("$and");
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supported_cell_types << "$mux" << "$pmux" << "$safe_pmux";
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supported_cell_types.insert("$or");
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supported_cell_types.insert("$xor");
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supported_cell_types.insert("$xnor");
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supported_cell_types.insert("$shl");
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supported_cell_types.insert("$shr");
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supported_cell_types.insert("$sshl");
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supported_cell_types.insert("$sshr");
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supported_cell_types.insert("$shift");
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supported_cell_types.insert("$shiftx");
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supported_cell_types.insert("$lt");
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supported_cell_types.insert("$le");
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supported_cell_types.insert("$eq");
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supported_cell_types.insert("$ne");
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supported_cell_types.insert("$eqx");
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supported_cell_types.insert("$nex");
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supported_cell_types.insert("$ge");
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supported_cell_types.insert("$gt");
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supported_cell_types.insert("$add");
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supported_cell_types.insert("$sub");
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// supported_cell_types.insert("$mul");
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// supported_cell_types.insert("$div");
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// supported_cell_types.insert("$mod");
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// supported_cell_types.insert("$pow");
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// supported_cell_types.insert("$mux");
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// supported_cell_types.insert("$pmux");
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// supported_cell_types.insert("$safe_pmux");
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}
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}
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};
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};
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@ -86,6 +61,72 @@ struct WreduceWorker
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WreduceWorker(WreduceConfig *config, Module *module) :
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WreduceWorker(WreduceConfig *config, Module *module) :
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config(config), module(module), mi(module) { }
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config(config), module(module), mi(module) { }
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void run_cell_mux(Cell *cell)
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{
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SigSpec sig_a = mi.sigmap(cell->getPort("\\A"));
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SigSpec sig_b = mi.sigmap(cell->getPort("\\B"));
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SigSpec sig_s = mi.sigmap(cell->getPort("\\S"));
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SigSpec sig_y = mi.sigmap(cell->getPort("\\Y"));
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std::vector<SigBit> bits_removed;
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for (int i = SIZE(sig_y)-1; i >= 0; i--)
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{
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auto info = mi.query(sig_y[i]);
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if (!info->is_output && SIZE(info->ports) <= 1) {
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bits_removed.push_back(Sx);
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continue;
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}
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SigBit ref = sig_a[i];
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for (int k = 0; k < SIZE(sig_s); k++) {
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if (ref != Sx && sig_b[k*SIZE(sig_a) + i] != Sx && ref != sig_b[k*SIZE(sig_a) + i])
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goto no_match_ab;
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if (sig_b[k*SIZE(sig_a) + i] != Sx)
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ref = sig_b[k*SIZE(sig_a) + i];
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}
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if (0)
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no_match_ab:
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break;
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bits_removed.push_back(ref);
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}
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if (!bits_removed.empty())
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{
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SigSpec sig_removed;
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for (int i = SIZE(bits_removed)-1; i >= 0; i--)
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sig_removed.append_bit(bits_removed[i]);
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log("Removed top %d bits (of %d) from mux cell %s.%s (%s).\n",
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SIZE(sig_removed), SIZE(sig_y), log_id(module), log_id(cell), log_id(cell->type));
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int n_removed = SIZE(sig_removed);
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int n_kept = SIZE(sig_y) - SIZE(sig_removed);
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SigSpec new_work_queue_bits;
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new_work_queue_bits.append(sig_a.extract(n_kept, n_removed));
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new_work_queue_bits.append(sig_y.extract(n_kept, n_removed));
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SigSpec new_sig_a = sig_a.extract(0, n_kept);
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SigSpec new_sig_y = sig_y.extract(0, n_kept);
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SigSpec new_sig_b;
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for (int k = 0; k < SIZE(sig_s); k++) {
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new_sig_b.append(sig_b.extract(k*SIZE(sig_a), n_kept));
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new_work_queue_bits.append(sig_b.extract(k*SIZE(sig_a) + n_kept, n_removed));
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}
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for (auto bit : new_work_queue_bits)
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work_queue_bits.insert(bit);
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cell->setPort("\\A", new_sig_a);
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cell->setPort("\\B", new_sig_b);
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cell->setPort("\\Y", new_sig_y);
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cell->fixup_parameters();
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module->connect(sig_y.extract(n_kept, n_removed), sig_removed);
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}
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}
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void run_reduce_inport(Cell *cell, char port)
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void run_reduce_inport(Cell *cell, char port)
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{
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{
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bool is_signed = cell->getParam(stringf("\\%c_SIGNED", port)).as_bool();
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bool is_signed = cell->getParam(stringf("\\%c_SIGNED", port)).as_bool();
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@ -112,6 +153,11 @@ struct WreduceWorker
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if (!cell->type.in(config->supported_cell_types))
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if (!cell->type.in(config->supported_cell_types))
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return;
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return;
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if (cell->type.in("$mux", "$pmux", "$safe_pmux")) {
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run_cell_mux(cell);
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return;
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}
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if (cell->type.in("$shl", "$shr", "$sshl", "$sshr"))
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if (cell->type.in("$shl", "$shr", "$sshl", "$sshr"))
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cell->setParam("\\B_SIGNED", false);
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cell->setParam("\\B_SIGNED", false);
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