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Define YOSYS and SYNTHESIS in preproc

This commit is contained in:
Clifford Wolf 2015-01-02 17:11:54 +01:00
parent 474831643c
commit 1bd67d792e
1 changed files with 2 additions and 1 deletions
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3
frontends/verilog/preproc.cc
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@ -221,7 +221,8 @@ std::string frontend_verilog_preproc(std::istream &f, std::string filename, cons
input_buffer_charp = 0; input_buffer_charp = 0;
input_file(f, filename); input_file(f, filename);
defines_map["__YOSYS__"] = "1"; defines_map["YOSYS"] = "1";
defines_map["SYNTHESIS"] = "1";
while (!input_buffer.empty()) while (!input_buffer.empty())
{ {