riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Clarify

This commit is contained in:
Eddie Hung 2019-09-19 21:58:34 -07:00
parent 34f9a8ceb2
commit 1b88211ec6
1 changed files with 2 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
passes/pmgen/xilinx_dsp.cc
View File

@ -507,7 +507,8 @@ struct XilinxDspPass : public Pass {
log("\n"); log("\n");
log("Multiply-accumulate operations using the post-adder with feedback on the 'C'\n"); log("Multiply-accumulate operations using the post-adder with feedback on the 'C'\n");
log("input will be folded into the DSP. In this scenario only, the 'C' input can be\n"); log("input will be folded into the DSP. In this scenario only, the 'C' input can be\n");
log("used to override the existing accumulation result with a new value.\n"); log("used to override the current accumulation result with a new value, which will\n");
log("be added to the multiplier result to form the next accumulation result.\n");
log("\n"); log("\n");
log("Use of the dedicated 'PCOUT' -> 'PCIN' cascade path is detected for 'P' -> 'C'\n"); log("Use of the dedicated 'PCOUT' -> 'PCIN' cascade path is detected for 'P' -> 'C'\n");
log("connections (optionally, where 'P' is right-shifted by 18-bits and used as an\n"); log("connections (optionally, where 'P' is right-shifted by 18-bits and used as an\n");