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machxo2: Add FACADE_SLICE simulation model.

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William D. Jones 2020-11-21 11:53:30 -05:00 committed by Marcelina Kościelnicka
parent cc52eb53cd
commit 1b703d3f03
1 changed files with 83 additions and 0 deletions
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83
techlibs/machxo2/cells_sim.v
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@ -68,3 +68,86 @@ module FACADE_FF #(
end
endgenerate
endmodule
module PFUMX (input ALUT, BLUT, C0, output Z);
assign Z = C0 ? ALUT : BLUT;
endmodule
module L6MUX21 (input D0, D1, SD, output Z);
assign Z = SD ? D1 : D0;
endmodule
/* For consistency, input order matches TRELLIS_SLICE even though the BELs in
prjtrellis were filled in clockwise order from bottom left. */
module FACADE_SLICE #(
parameter MODE = "LOGIC",
parameter GSR = "ENABLED",
parameter SRMODE = "LSR_OVER_CE",
parameter CEMUX = "1",
parameter CLKMUX = "0",
parameter LSRMUX = "LSR",
parameter LSRONMUX = "LSRMUX",
parameter LUT0_INITVAL = 16'hFFFF,
parameter LUT1_INITVAL = 16'hFFFF,
parameter REG0_SD = "1",
parameter REG1_SD = "1",
parameter REG0_REGSET = "SET",
parameter REG1_REGSET = "SET",
parameter REG0_REGMODE = "FF",
parameter REG1_REGMODE = "FF",
parameter CCU2_INJECT1_0 = "YES",
parameter CCU2_INJECT1_1 = "YES",
parameter WREMUX = "INV"
) (
input A0, B0, C0, D0,
input A1, B1, C1, D1,
input M0, M1,
input FCI, FXA, FXB,
input CLK, LSR, CE,
input DI0, DI1,
input WD0, WD1,
input WAD0, WAD1, WAD2, WAD3,
input WRE, WCK,
output F0, Q0,
output F1, Q1,
output FCO, OFX0, OFX1,
output WDO0, WDO1, WDO2, WDO3,
output WADO0, WADO1, WADO2, WADO3
);
generate
if (MODE == "LOGIC") begin
L6MUX21 FXMUX (.D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1));
wire k0;
wire k1;
PFUMX K0K1MUX (.ALUT(k1), .BLUT(k0), .C0(M0), .Z(OFX1));
LUT4 #(.INIT(LUT0_INITVAL)) LUT_0 (.A(A0), .B(B0), .C(C0), .D(D0), .Z(k0));
LUT4 #(.INIT(LUT0_INITVAL)) LUT_1 (.A(A0), .B(B0), .C(C0), .D(D0), .Z(k1));
assign F0 = k0;
assign F1 = k1;
end else if (MODE == "CCU2") begin
ERROR_UNSUPPORTED_SLICE_MODE error();
end else if (MODE == "DPRAM") begin
ERROR_UNSUPPORTED_SLICE_MODE error();
end else begin
ERROR_UNKNOWN_SLICE_MODE error();
end
endgenerate
wire di0 = (REG0_SD == "1") ? M0 : DI0;
wire di1 = (REG0_SD == "1") ? M1 : DI1;
FACADE_FF#(.GSR(GSR), .CEMUX(CEMUX), .CLKMUX(CLKMUX), .LSRMUX(LSRMUX),
.LSRONMUX(LSRONMUX), .SRMODE(SRMODE), .REGSET(REG0_REGSET),
.REGMODE(REG0_REGMODE)) REG_0 (.CLK(CLK), .DI(di0), .LSR(LSR), .CE(CE), .Q(Q0));
FACADE_FF#(.GSR(GSR), .CEMUX(CEMUX), .CLKMUX(CLKMUX), .LSRMUX(LSRMUX),
.LSRONMUX(LSRONMUX), .SRMODE(SRMODE), .REGSET(REG1_REGSET),
.REGMODE(REG1_REGMODE)) REG_1 (.CLK(CLK), .DI(di1), .LSR(LSR), .CE(CE), .Q(Q1));
endmodule