diff --git a/passes/pmgen/peepopt_muldiv_c.pmg b/passes/pmgen/peepopt_muldiv_c.pmg
index 78b5e768a..fff4ad2a9 100644
--- a/passes/pmgen/peepopt_muldiv_c.pmg
+++ b/passes/pmgen/peepopt_muldiv_c.pmg
@@ -55,6 +55,7 @@ code
 	int c_const_int = c_const.as_int(c_const_signed);
 	int b_const_int_shifted = b_const_int << offset;
 
+	// Integer values should be lesser than 64 bits
 	if (mul->getParam(ID::B_WIDTH).size() > 64)
 		reject;
 	if (b_const.size() > 64)
@@ -62,6 +63,11 @@ code
 	if (c_const.size() > 64)
 		reject;
 
+	// Check for potential mult overflow
+	if (b_const.size() + a.size() > mul_y.size()) {
+		reject;
+	}
+
 	// Check that there are only zeros before offset
 	if (offset < 0 || !div_a.extract(0, offset).is_fully_zero())
 		reject;
@@ -70,13 +76,6 @@ code
 	if (b_const_int_shifted % c_const_int != 0)
 		reject;
 
-	// Check that every single output bit of the multiplier is connected consecutively to the div operator (offset accounted for)
-	for (int i = 0; i < mul_y.size(); i++) {
-		if (sigmap(mul_y[i]) != sigmap(div_a[i + offset])) {
-			reject;
-		}
-	}
-
 	// Rewire to only keep multiplier
 	mul->setPort(\B, Const(b_const_int_shifted / c_const_int, b_const_width));
 	mul->setPort(\Y, div_y);
diff --git a/tests/peepopt/multdiv_c.ys b/tests/peepopt/multdiv_c.ys
index 6261b356f..fa8f0d38d 100644
--- a/tests/peepopt/multdiv_c.ys
+++ b/tests/peepopt/multdiv_c.ys
@@ -4,7 +4,7 @@ design -reset
 read_verilog <<EOF
 module top (
   input wire  [11:0] a,
-  output wire  [31:0] y
+  output wire  [11:0] y
 );
   assign y = (a * 16'd5140) / (257 * 2);
 endmodule
@@ -26,10 +26,10 @@ module top (
   output wire signed [31:0] y,
   output wire probe
 );
-   wire [44:0] tmp = (a * 16'd5140);
-   assign probe = tmp[44];
+   wire [28:0] tmp = (a * 16'd5140);
+   assign probe = tmp[28];
 
-  assign y = tmp[43:0] / (257 * 2);
+  assign y = tmp[27:0] / (257 * 2);
 endmodule
 EOF
 check -assert