mirror of https://github.com/YosysHQ/yosys.git
Add support for EDIF file reading using Verific
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parent
f5e2c0a498
commit
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5
Makefile
5
Makefile
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@ -18,6 +18,7 @@ ENABLE_READLINE := 1
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ENABLE_EDITLINE := 0
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ENABLE_GHDL := 0
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ENABLE_VERIFIC := 0
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ENABLE_VERIFIC_EDIF := 0
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DISABLE_VERIFIC_EXTENSIONS := 0
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DISABLE_VERIFIC_VHDL := 0
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ENABLE_COVER := 1
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@ -527,6 +528,10 @@ ifneq ($(wildcard $(VERIFIC_DIR)/vhdl),)
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VERIFIC_COMPONENTS += vhdl
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endif
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endif
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ifeq ($(ENABLE_VERIFIC_EDIF),1)
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VERIFIC_COMPONENTS += edif
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CXXFLAGS += -DVERIFIC_EDIF_SUPPORT
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endif
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ifneq ($(DISABLE_VERIFIC_EXTENSIONS),1)
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VERIFIC_COMPONENTS += extensions
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CXXFLAGS += -DYOSYSHQ_VERIFIC_EXTENSIONS
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@ -53,6 +53,10 @@ USING_YOSYS_NAMESPACE
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#include "VhdlUnits.h"
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#endif
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#ifdef VERIFIC_EDIF_SUPPORT
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#include "edif_file.h"
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#endif
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#include "VerificStream.h"
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#include "FileSystem.h"
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@ -2351,6 +2355,9 @@ void verific_import(Design *design, const std::map<std::string,std::string> &par
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veri_file::Reset();
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#ifdef VERIFIC_VHDL_SUPPORT
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vhdl_file::Reset();
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#endif
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#ifdef VERIFIC_EDIF_SUPPORT
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edif_file::Reset();
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#endif
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Libset::Reset();
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Message::Reset();
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@ -2412,6 +2419,13 @@ struct VerificPass : public Pass {
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log("Load the specified VHDL files into Verific.\n");
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log("\n");
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log("\n");
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#endif
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#ifdef VERIFIC_EDIF_SUPPORT
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log(" verific {-edif} <edif-file>..\n");
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log("\n");
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log("Load the specified EDIF files into Verific.\n");
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log("\n");
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log("\n");
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#endif
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log(" verific {-f|-F} [-vlog95|-vlog2k|-sv2005|-sv2009|\n");
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log(" -sv2012|-sv|-formal] <command-file>\n");
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@ -2958,7 +2972,18 @@ struct VerificPass : public Pass {
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goto check_error;
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}
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#endif
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#ifdef VERIFIC_EDIF_SUPPORT
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if (GetSize(args) > argidx && args[argidx] == "-edif") {
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edif_file edif;
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argidx++;
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while (argidx < GetSize(args)) {
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std::string filename = frontent_rewrite(args, argidx, tmp_files);
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if (!edif.Read(filename.c_str()))
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log_cmd_error("Reading `%s' in EDIF mode failed.\n", filename.c_str());
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}
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goto check_error;
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}
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#endif
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if (argidx < GetSize(args) && args[argidx] == "-pp")
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{
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const char* filename = nullptr;
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@ -3221,6 +3246,9 @@ struct VerificPass : public Pass {
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veri_file::Reset();
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#ifdef VERIFIC_VHDL_SUPPORT
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vhdl_file::Reset();
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#endif
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#ifdef VERIFIC_EDIF_SUPPORT
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edif_file::Reset();
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#endif
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Libset::Reset();
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Message::Reset();
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@ -3347,6 +3375,13 @@ struct ReadPass : public Pass {
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log("Load the specified VHDL files. (Requires Verific.)\n");
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log("\n");
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log("\n");
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#endif
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#ifdef VERIFIC_EDIF_SUPPORT
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log(" read {-edif} <edif-file>..\n");
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log("\n");
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log("Load the specified EDIF files. (Requires Verific.)\n");
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log("\n");
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log("\n");
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#endif
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log(" read {-f|-F} <command-file>\n");
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log("\n");
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@ -3440,6 +3475,17 @@ struct ReadPass : public Pass {
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}
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return;
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}
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#endif
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#ifdef VERIFIC_EDIF_SUPPORT
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if (args[1] == "-edif") {
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if (use_verific) {
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args[0] = "verific";
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Pass::call(design, args);
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} else {
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cmd_error(args, 1, "This version of Yosys is built without Verific support.\n");
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}
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return;
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}
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#endif
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if (args[1] == "-f" || args[1] == "-F") {
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if (use_verific) {
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