diff --git a/techlibs/nanoxplore/cells_sim_u.v b/techlibs/nanoxplore/cells_sim_u.v index 209da3b5f..c2c9c8b34 100644 --- a/techlibs/nanoxplore/cells_sim_u.v +++ b/techlibs/nanoxplore/cells_sim_u.v @@ -136,13 +136,38 @@ module NX_RFB_U(WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14 localparam MEM_SIZE = mode == 2 ? 64 : 32; localparam MEM_WIDTH = mode == 3 ? 36 : 18; localparam ADDR_WIDTH = mode == 2 ? 6 : 5; + localparam DATA_SIZE = MEM_SIZE * MEM_WIDTH; + localparam MAX_SIZE = DATA_SIZE + MEM_SIZE + 1; reg [MEM_WIDTH-1:0] mem [MEM_SIZE-1:0]; + function [DATA_SIZE-1:0] convert_initval; + input [8*MAX_SIZE-1:0] hex_initval; + reg done; + reg [DATA_SIZE-1:0] temp; + reg [7:0] char; + integer i,j; + begin + done = 1'b0; + temp = 0; + j = 0; + for (i = 0; i < MAX_SIZE; i = i + 1) begin + char = hex_initval[8*i +: 8]; + if (char >= "0" && char <= "1") begin + temp[j] = char - "0"; + j = j + 1; + end + end + convert_initval = temp; + end + endfunction + integer i; + reg [DATA_SIZE-1:0] mem_data; initial begin + mem_data = convert_initval(mem_ctxt); for (i = 0; i < MEM_SIZE; i = i + 1) - mem[i] = 36'b0; + mem[i] = mem_data[MEM_WIDTH*(MEM_SIZE-i-1) +: MEM_WIDTH]; end wire [ADDR_WIDTH-1:0] WA = (mode==2) ? { WA6, WA5, WA4, WA3, WA2, WA1 } : { WA5, WA4, WA3, WA2, WA1 }; diff --git a/techlibs/nanoxplore/rf_rams_u.txt b/techlibs/nanoxplore/rf_rams_u.txt index 3dd3d3614..94e002eeb 100644 --- a/techlibs/nanoxplore/rf_rams_u.txt +++ b/techlibs/nanoxplore/rf_rams_u.txt @@ -25,7 +25,6 @@ ram distributed $__NX_RFB_U_DPREG_ { widths 36 global; } init no_undef; - prune_rom; port sw "W" { clock anyedge; @@ -43,7 +42,6 @@ ram distributed $__NX_RFB_U_SPREG_ { abits 5; width 18; init no_undef; - prune_rom; port arsw "RW" { clock anyedge; } @@ -58,7 +56,6 @@ ram distributed $__NX_XRFB_2R_1W_ { abits 5; width 18; init no_undef; - prune_rom; port sw "W" { clock anyedge; } diff --git a/tests/arch/nanoxplore/meminit.v b/tests/arch/nanoxplore/meminit.v new file mode 100644 index 000000000..24d5a57f7 --- /dev/null +++ b/tests/arch/nanoxplore/meminit.v @@ -0,0 +1,50 @@ +module top(clk); +parameter DEPTH_LOG2 = 10; +parameter WIDTH = 36; +parameter PRIME = 237481091; +localparam DEPTH = 2**DEPTH_LOG2; + +input wire clk; + +(* syn_ramstyle = "distributed" *) +reg [WIDTH-1:0] mem [DEPTH-1:0]; + +integer i; +initial begin + for (i = 0; i < DEPTH; i = i + 1) begin + // Make up data by multiplying a large prime with the address, + // then cropping and retaining the lower bits + mem[i] = PRIME * (i*2+1); + end +end + +reg [DEPTH_LOG2-1:0] counter = 0; +reg done = 1'b0; + +reg did_read = 1'b0; +reg [DEPTH_LOG2-1:0] read_addr; +reg [WIDTH-1:0] read_val; + +always @(posedge clk) begin + if (!done) begin + did_read <= 1'b1; + read_addr <= counter; + read_val <= mem[counter]; + end else begin + did_read <= 1'b0; + end + + if (!done) + counter = counter + 1; + if (counter == 0) + done = 1; +end + +wire [WIDTH-1:0] expect_val = PRIME * (read_addr*2+1); +always @(posedge clk) begin + if (did_read) begin + $display("addr %x expected %x actual %x", read_addr, expect_val, read_val); + assert(read_val == expect_val); + end +end +endmodule diff --git a/tests/arch/nanoxplore/meminit.ys b/tests/arch/nanoxplore/meminit.ys new file mode 100644 index 000000000..ca93e6500 --- /dev/null +++ b/tests/arch/nanoxplore/meminit.ys @@ -0,0 +1,44 @@ +read_verilog -sv meminit.v +chparam -set DEPTH_LOG2 5 -set WIDTH 36 +prep +opt_dff +prep -rdff +synth_nanoxplore +clean_zerowidth +select -assert-none t:$mem_v2 t:$mem +read_verilog +/nanoxplore/cells_sim.v +/nanoxplore/cells_sim_u.v +prep +async2sync +hierarchy -top top +sim -assert -q -n 66 -clock clk + +design -reset +read_verilog -sv meminit.v +chparam -set DEPTH_LOG2 6 -set WIDTH 18 +prep +opt_dff +prep -rdff +synth_nanoxplore +clean_zerowidth +select -assert-none t:$mem_v2 t:$mem +read_verilog +/nanoxplore/cells_sim.v +/nanoxplore/cells_sim_u.v +prep +async2sync +hierarchy -top top +sim -assert -q -n 34 -clock clk + + +design -reset +read_verilog -sv meminit.v +chparam -set DEPTH_LOG2 8 -set WIDTH 18 +prep +opt_dff +prep -rdff +synth_nanoxplore +clean_zerowidth +select -assert-none t:$mem_v2 t:$mem +read_verilog +/nanoxplore/cells_sim.v +/nanoxplore/cells_sim_u.v +prep +async2sync +hierarchy -top top +sim -assert -q -n 258 -clock clk