techmap: add TCL test for Han-Carlson adder

This commit is contained in:
Emil J. Tywoniak 2024-11-28 15:16:48 +01:00
parent 289673a807
commit 1a562f9605
4 changed files with 37 additions and 1 deletions

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yosys -import
read_verilog +/choices/han-carlson.v
read_verilog lcu_refined.v
design -save init
for {set i 1} {$i <= 16} {incr i} {
design -load init
chparam -set WIDTH $i
yosys proc
equiv_make -blacklist han-carlson.nomatch lcu _85_lcu_han_carlson equiv
equiv_simple equiv
equiv_status -assert equiv
}

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// Copied from techlibs/common/simlib.v
// with this condition removed: (^{P, G, CI} !== 1'bx)
module lcu (P, G, CI, CO);
parameter WIDTH = 2;
input [WIDTH-1:0] P; // Propagate
input [WIDTH-1:0] G; // Generate
input CI; // Carry-in
output reg [WIDTH-1:0] CO; // Carry-out
integer i;
always @* begin
CO[0] = G[0] || (P[0] && CI);
for (i = 1; i < WIDTH; i = i+1)
CO[i] = G[i] || (P[i] && CO[i-1]);
end
endmodule

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#!/usr/bin/env bash #!/usr/bin/env bash
set -eu set -eu
source ../gen-tests-makefile.sh source ../gen-tests-makefile.sh
run_tests --yosys-scripts --bash --yosys-args "-e 'select out of bounds'" run_tests --yosys-scripts --tcl-scripts --bash --yosys-args "-e 'select out of bounds'"