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remove not needed top module

This commit is contained in:
Miodrag Milanovic 2019-10-04 09:39:34 +02:00
parent a198bcdd4f
commit 1a399c6456
2 changed files with 2 additions and 17 deletions
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15
tests/xilinx/tribuf.v
View File

@ -6,18 +6,3 @@ module tristate (en, i, o);
always @(en or i) always @(en or i)
o <= (en)? i : 1'bZ; o <= (en)? i : 1'bZ;
endmodule endmodule
module top (
input en,
input a,
output b
);
tristate u_tri (
.en (en ),
.i (a ),
.o (b )
);
endmodule

4
tests/xilinx/tribuf.ys
View File

@ -1,12 +1,12 @@
read_verilog tribuf.v read_verilog tribuf.v
hierarchy -top top hierarchy -top tristate
proc proc
tribuf tribuf
flatten flatten
synth synth
equiv_opt -assert -map +/xilinx/cells_sim.v -map +/simcells.v synth_xilinx # equivalency check equiv_opt -assert -map +/xilinx/cells_sim.v -map +/simcells.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module cd tristate # Constrain all select calls below inside the top module
# TODO :: Tristate logic not yet supported; see https://github.com/YosysHQ/yosys/issues/1225 # TODO :: Tristate logic not yet supported; see https://github.com/YosysHQ/yosys/issues/1225
select -assert-count 1 t:$_TBUF_ select -assert-count 1 t:$_TBUF_
select -assert-none t:$_TBUF_ %% t:* %D select -assert-none t:$_TBUF_ %% t:* %D