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use output reg instead of additional reg declaration

This commit is contained in:
chunlin min 2024-07-04 14:13:26 -04:00
parent 7ff8912338
commit 19d3214861
1 changed files with 6 additions and 14 deletions
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20
techlibs/microchip/cells_sim.v
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@ -164,22 +164,18 @@ module MICROCHIP_SYNC_SET_DFF(
input CLK, input CLK,
input Set, input Set,
input En, input En,
output Q); output reg Q);
parameter [0:0] INIT = 1'b0; // unused parameter [0:0] INIT = 1'b0; // unused
reg q_ff;
always @(posedge CLK) begin always @(posedge CLK) begin
if (En == 1) begin if (En == 1) begin
if (Set == 0) if (Set == 0)
q_ff <= 1; Q <= 1;
else else
q_ff <= D; Q <= D;
end end
end end
assign Q = q_ff;
specify specify
$setup(D , posedge CLK &&& En && Set, 0); // neg setup not supported? $setup(D , posedge CLK &&& En && Set, 0); // neg setup not supported?
$setup(En, posedge CLK, 109); $setup(En, posedge CLK, 109);
@ -195,22 +191,18 @@ module MICROCHIP_SYNC_RESET_DFF(
input CLK, input CLK,
input Reset, input Reset,
input En, input En,
output Q); output reg Q);
parameter [0:0] INIT = 1'b0; // unused parameter [0:0] INIT = 1'b0; // unused
reg q_ff;
always @(posedge CLK) begin always @(posedge CLK) begin
if (En == 1) begin if (En == 1) begin
if (Reset == 0) if (Reset == 0)
q_ff <= 0; Q <= 0;
else else
q_ff <= D; Q <= D;
end end
end end
assign Q = q_ff;
specify specify
$setup(D , posedge CLK &&& En && Reset, 0); // neg setup not supported? $setup(D , posedge CLK &&& En && Reset, 0); // neg setup not supported?
$setup(En, posedge CLK, 109); $setup(En, posedge CLK, 109);