mirror of https://github.com/YosysHQ/yosys.git
Add "verific -vlog-libdir"
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1954c78ea7
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@ -1856,6 +1856,12 @@ struct VerificPass : public Pass {
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log("Add Verilog include directories.\n");
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log("Add Verilog include directories.\n");
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log("\n");
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log("\n");
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log("\n");
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log("\n");
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log(" verific -vlog-libdir <directory>..\n");
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log("\n");
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log("Add Verilog library directories. Verific will search in this directories to\n");
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log("find undefined modules.\n");
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log("\n");
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log("\n");
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log(" verific -vlog-define <macro>[=<value>]..\n");
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log(" verific -vlog-define <macro>[=<value>]..\n");
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log("\n");
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log("\n");
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log("Add Verilog defines. (The macros SYNTHESIS and VERIFIC are defined implicitly.)\n");
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log("Add Verilog defines. (The macros SYNTHESIS and VERIFIC are defined implicitly.)\n");
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@ -1942,6 +1948,12 @@ struct VerificPass : public Pass {
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goto check_error;
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goto check_error;
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}
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}
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if (GetSize(args) > argidx && args[argidx] == "-vlog-libdir") {
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for (argidx++; argidx < GetSize(args); argidx++)
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veri_file::AddYDir(args[argidx].c_str());
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goto check_error;
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}
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if (GetSize(args) > argidx && args[argidx] == "-vlog-define") {
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if (GetSize(args) > argidx && args[argidx] == "-vlog-define") {
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for (argidx++; argidx < GetSize(args); argidx++) {
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for (argidx++; argidx < GetSize(args); argidx++) {
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string name = args[argidx];
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string name = args[argidx];
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