From 550310e2647c7aac1e49b79d9ff912436103062f Mon Sep 17 00:00:00 2001 From: whitequark Date: Wed, 1 Jan 2020 12:30:00 +0000 Subject: [PATCH 1/2] Harmonize BRAM/LUTRAM descriptions across all of Yosys. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This commit: * renames all remaining instances of "DRAM" (which is ambiguous) to "LUTRAM" (which is not), finishing the work started in the commit 698ab9be; * renames memory rule files to brams.txt/lutrams.txt; * adds/renames script labels map_bram/map_lutram; * extracts where necessary script labels map_ffram and map_gates; * adds where necessary options -nobram/-nolutram. The end result is that BRAM/LUTRAM/FFRAM aspects of every target are now consistent with each other. Per architecture: * anlogic: rename drams.txt→lutrams.txt, add -nolutram, add :map_lutram, :map_ffram, :map_gates * ecp5: rename bram.txt→brams.txt, lutram.txt→lutrams.txt * efinix: rename bram.txt→brams.txt, add -nobram, add :map_ffram, :map_gates * gowin: rename bram.txt→brams.txt, dram.txt→lutrams.txt, rename -nodram→-nolutram (-nodram still recognized), rename :bram→:map_bram, :dram→:map_lutram, add :map_ffram, :map_gates --- techlibs/anlogic/Makefile.inc | 6 ++--- ...{dram_init_16x4.vh => lutram_init_16x4.vh} | 0 techlibs/anlogic/{drams.txt => lutrams.txt} | 0 .../anlogic/{drams_map.v => lutrams_map.v} | 2 +- techlibs/anlogic/synth_anlogic.cc | 24 ++++++++++++----- techlibs/ecp5/Makefile.inc | 4 +-- techlibs/ecp5/{bram.txt => brams.txt} | 0 techlibs/ecp5/{lutram.txt => lutrams.txt} | 0 techlibs/ecp5/synth_ecp5.cc | 4 +-- techlibs/efinix/Makefile.inc | 2 +- techlibs/efinix/{bram.txt => brams.txt} | 0 techlibs/efinix/synth_efinix.cc | 22 +++++++++++---- techlibs/gowin/Makefile.inc | 6 ++--- techlibs/gowin/{bram.txt => brams.txt} | 0 techlibs/gowin/{dram.txt => lutrams.txt} | 0 techlibs/gowin/{drams_map.v => lutrams_map.v} | 0 techlibs/gowin/synth_gowin.cc | 27 ++++++++++--------- techlibs/intel/synth_intel.cc | 10 +++---- 18 files changed, 67 insertions(+), 40 deletions(-) rename techlibs/anlogic/{dram_init_16x4.vh => lutram_init_16x4.vh} (100%) rename techlibs/anlogic/{drams.txt => lutrams.txt} (100%) rename techlibs/anlogic/{drams_map.v => lutrams_map.v} (91%) rename techlibs/ecp5/{bram.txt => brams.txt} (100%) rename techlibs/ecp5/{lutram.txt => lutrams.txt} (100%) rename techlibs/efinix/{bram.txt => brams.txt} (100%) rename techlibs/gowin/{bram.txt => brams.txt} (100%) rename techlibs/gowin/{dram.txt => lutrams.txt} (100%) rename techlibs/gowin/{drams_map.v => lutrams_map.v} (100%) diff --git a/techlibs/anlogic/Makefile.inc b/techlibs/anlogic/Makefile.inc index 9426b5ca5..2d8d65e2e 100644 --- a/techlibs/anlogic/Makefile.inc +++ b/techlibs/anlogic/Makefile.inc @@ -7,6 +7,6 @@ $(eval $(call add_share_file,share/anlogic,techlibs/anlogic/cells_map.v)) $(eval $(call add_share_file,share/anlogic,techlibs/anlogic/arith_map.v)) $(eval $(call add_share_file,share/anlogic,techlibs/anlogic/cells_sim.v)) $(eval $(call add_share_file,share/anlogic,techlibs/anlogic/eagle_bb.v)) -$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/drams.txt)) -$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/drams_map.v)) -$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/dram_init_16x4.vh)) +$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/lutrams.txt)) +$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/lutrams_map.v)) +$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/lutram_init_16x4.vh)) diff --git a/techlibs/anlogic/dram_init_16x4.vh b/techlibs/anlogic/lutram_init_16x4.vh similarity index 100% rename from techlibs/anlogic/dram_init_16x4.vh rename to techlibs/anlogic/lutram_init_16x4.vh diff --git a/techlibs/anlogic/drams.txt b/techlibs/anlogic/lutrams.txt similarity index 100% rename from techlibs/anlogic/drams.txt rename to techlibs/anlogic/lutrams.txt diff --git a/techlibs/anlogic/drams_map.v b/techlibs/anlogic/lutrams_map.v similarity index 91% rename from techlibs/anlogic/drams_map.v rename to techlibs/anlogic/lutrams_map.v index 084e2a25f..5a464cafc 100644 --- a/techlibs/anlogic/drams_map.v +++ b/techlibs/anlogic/lutrams_map.v @@ -10,7 +10,7 @@ module \$__ANLOGIC_DRAM16X4 (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); input B1EN; EG_LOGIC_DRAM16X4 #( - `include "dram_init_16x4.vh" + `include "lutram_init_16x4.vh" ) _TECHMAP_REPLACE_ ( .di(B1DATA), .waddr(B1ADDR), diff --git a/techlibs/anlogic/synth_anlogic.cc b/techlibs/anlogic/synth_anlogic.cc index b87fc8566..3a1992588 100644 --- a/techlibs/anlogic/synth_anlogic.cc +++ b/techlibs/anlogic/synth_anlogic.cc @@ -60,6 +60,9 @@ struct SynthAnlogicPass : public ScriptPass log(" -retime\n"); log(" run 'abc' with -dff option\n"); log("\n"); + log(" -nolutram\n"); + log(" do not use EG_LOGIC_DRAM16X4 cells in output netlist\n"); + log("\n"); log("\n"); log("The following commands are executed by this synthesis command:\n"); help_script(); @@ -67,7 +70,7 @@ struct SynthAnlogicPass : public ScriptPass } string top_opt, edif_file, json_file; - bool flatten, retime; + bool flatten, retime, nolutram; void clear_flags() YS_OVERRIDE { @@ -76,6 +79,7 @@ struct SynthAnlogicPass : public ScriptPass json_file = ""; flatten = true; retime = false; + nolutram = false; } void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE @@ -110,6 +114,10 @@ struct SynthAnlogicPass : public ScriptPass flatten = false; continue; } + if (args[argidx] == "-nolutram") { + nolutram = true; + continue; + } if (args[argidx] == "-retime") { retime = true; continue; @@ -150,18 +158,22 @@ struct SynthAnlogicPass : public ScriptPass run("synth -run coarse"); } - if (check_label("dram")) + if (!nolutram && check_label("map_lutram", "(skip if -nolutram)")) { - run("memory_bram -rules +/anlogic/drams.txt"); - run("techmap -map +/anlogic/drams_map.v"); + run("memory_bram -rules +/anlogic/lutrams.txt"); + run("techmap -map +/anlogic/lutrams_map.v"); run("setundef -zero -params t:EG_LOGIC_DRAM16X4"); } - if (check_label("fine")) + if (check_label("map_ffram")) { run("opt -fast -mux_undef -undriven -fine"); run("memory_map"); run("opt -undriven -fine"); + } + + if (check_label("map_gates")) + { run("techmap -map +/techmap.v -map +/anlogic/arith_map.v"); if (retime || help_mode) run("abc -dff", "(only if -retime)"); @@ -187,7 +199,7 @@ struct SynthAnlogicPass : public ScriptPass run("techmap -map +/anlogic/cells_map.v"); run("clean"); } - + if (check_label("map_anlogic")) { run("anlogic_fixcarry"); diff --git a/techlibs/ecp5/Makefile.inc b/techlibs/ecp5/Makefile.inc index 46463f510..2c33f23b9 100644 --- a/techlibs/ecp5/Makefile.inc +++ b/techlibs/ecp5/Makefile.inc @@ -8,9 +8,9 @@ $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_map.v)) $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_sim.v)) $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_bb.v)) $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/lutrams_map.v)) -$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/lutram.txt)) +$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/lutrams.txt)) $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/brams_map.v)) -$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/bram.txt)) +$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/brams.txt)) $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/arith_map.v)) $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/latches_map.v)) $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/dsp_map.v)) diff --git a/techlibs/ecp5/bram.txt b/techlibs/ecp5/brams.txt similarity index 100% rename from techlibs/ecp5/bram.txt rename to techlibs/ecp5/brams.txt diff --git a/techlibs/ecp5/lutram.txt b/techlibs/ecp5/lutrams.txt similarity index 100% rename from techlibs/ecp5/lutram.txt rename to techlibs/ecp5/lutrams.txt diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc index a0ea6d1f9..3985da57a 100644 --- a/techlibs/ecp5/synth_ecp5.cc +++ b/techlibs/ecp5/synth_ecp5.cc @@ -266,13 +266,13 @@ struct SynthEcp5Pass : public ScriptPass if (!nobram && check_label("map_bram", "(skip if -nobram)")) { - run("memory_bram -rules +/ecp5/bram.txt"); + run("memory_bram -rules +/ecp5/brams.txt"); run("techmap -map +/ecp5/brams_map.v"); } if (!nolutram && check_label("map_lutram", "(skip if -nolutram)")) { - run("memory_bram -rules +/ecp5/lutram.txt"); + run("memory_bram -rules +/ecp5/lutrams.txt"); run("techmap -map +/ecp5/lutrams_map.v"); } diff --git a/techlibs/efinix/Makefile.inc b/techlibs/efinix/Makefile.inc index 5013f7fc1..69665982c 100644 --- a/techlibs/efinix/Makefile.inc +++ b/techlibs/efinix/Makefile.inc @@ -7,4 +7,4 @@ $(eval $(call add_share_file,share/efinix,techlibs/efinix/cells_map.v)) $(eval $(call add_share_file,share/efinix,techlibs/efinix/arith_map.v)) $(eval $(call add_share_file,share/efinix,techlibs/efinix/cells_sim.v)) $(eval $(call add_share_file,share/efinix,techlibs/efinix/brams_map.v)) -$(eval $(call add_share_file,share/efinix,techlibs/efinix/bram.txt)) +$(eval $(call add_share_file,share/efinix,techlibs/efinix/brams.txt)) diff --git a/techlibs/efinix/bram.txt b/techlibs/efinix/brams.txt similarity index 100% rename from techlibs/efinix/bram.txt rename to techlibs/efinix/brams.txt diff --git a/techlibs/efinix/synth_efinix.cc b/techlibs/efinix/synth_efinix.cc index 26a8d4eda..3e5274385 100644 --- a/techlibs/efinix/synth_efinix.cc +++ b/techlibs/efinix/synth_efinix.cc @@ -60,6 +60,9 @@ struct SynthEfinixPass : public ScriptPass log(" -retime\n"); log(" run 'abc' with -dff option\n"); log("\n"); + log(" -nobram\n"); + log(" do not use EFX_RAM_5K cells in output netlist\n"); + log("\n"); log("\n"); log("The following commands are executed by this synthesis command:\n"); help_script(); @@ -67,7 +70,7 @@ struct SynthEfinixPass : public ScriptPass } string top_opt, edif_file, json_file; - bool flatten, retime; + bool flatten, retime, nobram; void clear_flags() YS_OVERRIDE { @@ -76,6 +79,7 @@ struct SynthEfinixPass : public ScriptPass json_file = ""; flatten = true; retime = false; + nobram = false; } void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE @@ -114,6 +118,10 @@ struct SynthEfinixPass : public ScriptPass retime = true; continue; } + if (args[argidx] == "-nobram") { + nobram = true; + continue; + } break; } extra_args(args, argidx, design); @@ -150,18 +158,22 @@ struct SynthEfinixPass : public ScriptPass run("synth -run coarse"); } - if (check_label("map_bram", "(skip if -nobram)")) + if (!nobram || check_label("map_bram", "(skip if -nobram)")) { - run("memory_bram -rules +/efinix/bram.txt"); + run("memory_bram -rules +/efinix/brams.txt"); run("techmap -map +/efinix/brams_map.v"); run("setundef -zero -params t:EFX_RAM_5K"); } - if (check_label("fine")) + if (check_label("map_ffram")) { run("opt -fast -mux_undef -undriven -fine"); run("memory_map"); run("opt -undriven -fine"); + } + + if (check_label("map_gates")) + { run("techmap -map +/techmap.v -map +/efinix/arith_map.v"); if (retime || help_mode) run("abc -dff", "(only if -retime)"); @@ -194,7 +206,7 @@ struct SynthEfinixPass : public ScriptPass run("efinix_fixcarry"); run("clean"); } - + if (check_label("check")) { run("hierarchy -check"); diff --git a/techlibs/gowin/Makefile.inc b/techlibs/gowin/Makefile.inc index d2853704b..fe5d9d6e6 100644 --- a/techlibs/gowin/Makefile.inc +++ b/techlibs/gowin/Makefile.inc @@ -7,9 +7,9 @@ $(eval $(call add_share_file,share/gowin,techlibs/gowin/cells_map.v)) $(eval $(call add_share_file,share/gowin,techlibs/gowin/cells_sim.v)) $(eval $(call add_share_file,share/gowin,techlibs/gowin/arith_map.v)) $(eval $(call add_share_file,share/gowin,techlibs/gowin/brams_map.v)) -$(eval $(call add_share_file,share/gowin,techlibs/gowin/bram.txt)) -$(eval $(call add_share_file,share/gowin,techlibs/gowin/drams_map.v)) -$(eval $(call add_share_file,share/gowin,techlibs/gowin/dram.txt)) +$(eval $(call add_share_file,share/gowin,techlibs/gowin/brams.txt)) +$(eval $(call add_share_file,share/gowin,techlibs/gowin/lutrams_map.v)) +$(eval $(call add_share_file,share/gowin,techlibs/gowin/lutrams.txt)) diff --git a/techlibs/gowin/bram.txt b/techlibs/gowin/brams.txt similarity index 100% rename from techlibs/gowin/bram.txt rename to techlibs/gowin/brams.txt diff --git a/techlibs/gowin/dram.txt b/techlibs/gowin/lutrams.txt similarity index 100% rename from techlibs/gowin/dram.txt rename to techlibs/gowin/lutrams.txt diff --git a/techlibs/gowin/drams_map.v b/techlibs/gowin/lutrams_map.v similarity index 100% rename from techlibs/gowin/drams_map.v rename to techlibs/gowin/lutrams_map.v diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc index 6cf058f29..785f2802b 100644 --- a/techlibs/gowin/synth_gowin.cc +++ b/techlibs/gowin/synth_gowin.cc @@ -55,7 +55,7 @@ struct SynthGowinPass : public ScriptPass log(" -nobram\n"); log(" do not use BRAM cells in output netlist\n"); log("\n"); - log(" -nodram\n"); + log(" -nolutram\n"); log(" do not use distributed RAM cells in output netlist\n"); log("\n"); log(" -noflatten\n"); @@ -80,7 +80,7 @@ struct SynthGowinPass : public ScriptPass } string top_opt, vout_file; - bool retime, nobram, nodram, flatten, nodffe, nowidelut, abc9, noiopads; + bool retime, nobram, nolutram, flatten, nodffe, nowidelut, abc9, noiopads; void clear_flags() YS_OVERRIDE { @@ -90,7 +90,7 @@ struct SynthGowinPass : public ScriptPass flatten = true; nobram = false; nodffe = false; - nodram = false; + nolutram = false; nowidelut = false; abc9 = false; noiopads = false; @@ -128,8 +128,8 @@ struct SynthGowinPass : public ScriptPass nobram = true; continue; } - if (args[argidx] == "-nodram") { - nodram = true; + if (args[argidx] == "-nolutram" || /*deprecated*/args[argidx] == "-nodram") { + nolutram = true; continue; } if (args[argidx] == "-nodffe") { @@ -188,24 +188,28 @@ struct SynthGowinPass : public ScriptPass run("synth -run coarse"); } - if (!nobram && check_label("bram", "(skip if -nobram)")) + if (!nobram && check_label("map_bram", "(skip if -nobram)")) { - run("memory_bram -rules +/gowin/bram.txt"); + run("memory_bram -rules +/gowin/brams.txt"); run("techmap -map +/gowin/brams_map.v -map +/gowin/cells_sim.v"); } - if (!nodram && check_label("dram", "(skip if -nodram)")) + if (!nolutram && check_label("map_lutram", "(skip if -nolutram)")) { - run("memory_bram -rules +/gowin/dram.txt"); - run("techmap -map +/gowin/drams_map.v"); + run("memory_bram -rules +/gowin/lutrams.txt"); + run("techmap -map +/gowin/lutrams_map.v"); run("determine_init"); } - if (check_label("fine")) + if (check_label("map_ffram")) { run("opt -fast -mux_undef -undriven -fine"); run("memory_map"); run("opt -undriven -fine"); + } + + if (check_label("map_gates")) + { run("techmap -map +/techmap.v -map +/gowin/arith_map.v"); run("techmap -map +/techmap.v"); if (retime || help_mode) @@ -248,7 +252,6 @@ struct SynthGowinPass : public ScriptPass run("iopadmap -bits -inpad IBUF O:I -outpad OBUF I:O " "-toutpad TBUF OEN:I:O -tinoutpad IOBUF OEN:O:I:IO", "(unless -noiopads)"); run("clean"); - } if (check_label("check")) diff --git a/techlibs/intel/synth_intel.cc b/techlibs/intel/synth_intel.cc index c8c690e45..5aa1a12d4 100644 --- a/techlibs/intel/synth_intel.cc +++ b/techlibs/intel/synth_intel.cc @@ -187,10 +187,10 @@ struct SynthIntelPass : public ScriptPass { } if (!nobram && check_label("map_bram", "(skip if -nobram)")) { - if (family_opt == "cycloneiv" || - family_opt == "cycloneive" || - family_opt == "max10" || - help_mode) { + if (family_opt == "cycloneiv" || + family_opt == "cycloneive" || + family_opt == "max10" || + help_mode) { run("memory_bram -rules +/intel/common/brams_m9k.txt", "(if applicable for family)"); run("techmap -map +/intel/common/brams_map_m9k.v", "(if applicable for family)"); } else { @@ -224,7 +224,7 @@ struct SynthIntelPass : public ScriptPass { if (check_label("map_cells")) { if (iopads || help_mode) run("iopadmap -bits -outpad $__outpad I:O -inpad $__inpad O:I", "(if -iopads)"); - run(stringf("techmap -map +/intel/%s/cells_map.v", family_opt.c_str())); + run(stringf("techmap -map +/intel/%s/cells_map.v", family_opt.c_str())); run("dffinit -highlow -ff dffeas q power_up"); run("clean -purge"); } From c5d28f5d6b20a42e6f3a4b1a4e3be341a352e5e3 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Sat, 4 Jan 2020 19:00:44 +0100 Subject: [PATCH 2/2] Valid to have attribute starting with SB_CARRY. --- techlibs/ice40/ice40_opt.cc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc index 371ceb623..9bee0444b 100644 --- a/techlibs/ice40/ice40_opt.cc +++ b/techlibs/ice40/ice40_opt.cc @@ -128,6 +128,8 @@ static void run_ice40_opts(Module *module) new_attr.insert(std::make_pair(a.first, a.second)); else if (a.first.in(ID(SB_LUT4.name), ID::keep, ID(module_not_derived))) continue; + else if (a.first.begins_with("\\SB_CARRY.\\")) + continue; else log_abort(); cell->attributes = std::move(new_attr);