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fixed error

This commit is contained in:
Miodrag Milanovic 2019-10-18 13:15:36 +02:00
parent 9bd9db56c8
commit 190b40341a
1 changed files with 1 additions and 1 deletions
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2
tests/arch/common/counter.v
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@ -6,6 +6,6 @@ module top ( out, clk, reset );
always @(posedge clk, posedge reset) always @(posedge clk, posedge reset)
if (reset) if (reset)
out <= 8'b0; out <= 8'b0;
end else
out <= out + 1; out <= out + 1;
endmodule endmodule