mirror of https://github.com/YosysHQ/yosys.git
Merge pull request #3259 from YosysHQ/micko/verific_valgrind
Fix valgrind tests when using verific
This commit is contained in:
commit
18fb73fd89
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@ -2239,11 +2239,15 @@ void verific_import(Design *design, const std::map<std::string,std::string> &par
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nl_todo.erase(it);
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nl_todo.erase(it);
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}
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}
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hier_tree::DeleteHierarchicalTree();
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veri_file::Reset();
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veri_file::Reset();
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#ifdef VERIFIC_VHDL_SUPPORT
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#ifdef VERIFIC_VHDL_SUPPORT
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vhdl_file::Reset();
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vhdl_file::Reset();
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#endif
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#endif
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Libset::Reset();
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Libset::Reset();
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Message::Reset();
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RuntimeFlags::DeleteAllFlags();
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LineFile::DeleteAllLineFiles();
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verific_incdirs.clear();
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verific_incdirs.clear();
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verific_libdirs.clear();
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verific_libdirs.clear();
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verific_import_pending = false;
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verific_import_pending = false;
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@ -3248,11 +3252,15 @@ struct VerificPass : public Pass {
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nl_todo.erase(it);
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nl_todo.erase(it);
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}
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}
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hier_tree::DeleteHierarchicalTree();
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veri_file::Reset();
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veri_file::Reset();
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#ifdef VERIFIC_VHDL_SUPPORT
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#ifdef VERIFIC_VHDL_SUPPORT
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vhdl_file::Reset();
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vhdl_file::Reset();
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#endif
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#endif
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Libset::Reset();
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Libset::Reset();
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Message::Reset();
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RuntimeFlags::DeleteAllFlags();
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LineFile::DeleteAllLineFiles();
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verific_incdirs.clear();
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verific_incdirs.clear();
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verific_libdirs.clear();
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verific_libdirs.clear();
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verific_import_pending = false;
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verific_import_pending = false;
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@ -1,6 +1,6 @@
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`default_nettype none
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`default_nettype none
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module hierdefparam_top(input [7:0] A, output [7:0] Y);
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module hierdefparam_top(input wire [7:0] A, output wire [7:0] Y);
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generate begin:foo
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generate begin:foo
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hierdefparam_a mod_a(.A(A), .Y(Y));
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hierdefparam_a mod_a(.A(A), .Y(Y));
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end endgenerate
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end endgenerate
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@ -8,7 +8,7 @@ module hierdefparam_top(input [7:0] A, output [7:0] Y);
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defparam foo.mod_a.bar[1].mod_b.addvalue = 43;
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defparam foo.mod_a.bar[1].mod_b.addvalue = 43;
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endmodule
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endmodule
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module hierdefparam_a(input [7:0] A, output [7:0] Y);
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module hierdefparam_a(input wire [7:0] A, output wire [7:0] Y);
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genvar i;
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genvar i;
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generate
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generate
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for (i = 0; i < 2; i=i+1) begin:bar
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for (i = 0; i < 2; i=i+1) begin:bar
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@ -19,7 +19,7 @@ module hierdefparam_a(input [7:0] A, output [7:0] Y);
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assign bar[0].a = A, bar[1].a = bar[0].y, Y = bar[1].y;
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assign bar[0].a = A, bar[1].a = bar[0].y, Y = bar[1].y;
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endmodule
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endmodule
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module hierdefparam_b(input [7:0] A, output [7:0] Y);
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module hierdefparam_b(input wire [7:0] A, output wire [7:0] Y);
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parameter [7:0] addvalue = 44;
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parameter [7:0] addvalue = 44;
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assign Y = A + addvalue;
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assign Y = A + addvalue;
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endmodule
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endmodule
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@ -3,7 +3,7 @@
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module module_scope_Example(o1, o2);
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module module_scope_Example(o1, o2);
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parameter [31:0] v1 = 10;
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parameter [31:0] v1 = 10;
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parameter [31:0] v2 = 20;
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parameter [31:0] v2 = 20;
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output [31:0] o1, o2;
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output wire [31:0] o1, o2;
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assign module_scope_Example.o1 = module_scope_Example.v1;
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assign module_scope_Example.o1 = module_scope_Example.v1;
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assign module_scope_Example.o2 = module_scope_Example.v2;
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assign module_scope_Example.o2 = module_scope_Example.v2;
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endmodule
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endmodule
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@ -11,14 +11,14 @@ endmodule
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module module_scope_ExampleLong(o1, o2);
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module module_scope_ExampleLong(o1, o2);
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parameter [31:0] ThisIsAnExtremelyLongParameterNameToTriggerTheSHA1Checksum1 = 10;
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parameter [31:0] ThisIsAnExtremelyLongParameterNameToTriggerTheSHA1Checksum1 = 10;
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parameter [31:0] ThisIsAnExtremelyLongParameterNameToTriggerTheSHA1Checksum2 = 20;
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parameter [31:0] ThisIsAnExtremelyLongParameterNameToTriggerTheSHA1Checksum2 = 20;
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output [31:0] o1, o2;
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output wire [31:0] o1, o2;
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assign module_scope_ExampleLong.o1 = module_scope_ExampleLong.ThisIsAnExtremelyLongParameterNameToTriggerTheSHA1Checksum1;
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assign module_scope_ExampleLong.o1 = module_scope_ExampleLong.ThisIsAnExtremelyLongParameterNameToTriggerTheSHA1Checksum1;
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assign module_scope_ExampleLong.o2 = module_scope_ExampleLong.ThisIsAnExtremelyLongParameterNameToTriggerTheSHA1Checksum2;
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assign module_scope_ExampleLong.o2 = module_scope_ExampleLong.ThisIsAnExtremelyLongParameterNameToTriggerTheSHA1Checksum2;
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endmodule
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endmodule
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module module_scope_top(
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module module_scope_top(
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output [31:0] a1, a2, b1, b2, c1, c2,
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output wire [31:0] a1, a2, b1, b2, c1, c2,
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output [31:0] d1, d2, e1, e2, f1, f2
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output wire [31:0] d1, d2, e1, e2, f1, f2
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);
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);
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module_scope_Example a(a1, a2);
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module_scope_Example a(a1, a2);
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module_scope_Example #(1) b(b1, b2);
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module_scope_Example #(1) b(b1, b2);
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@ -1,4 +1,4 @@
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module test_specify;
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module test_specify(input A, output B);
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specparam a=1;
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specparam a=1;
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