Merge pull request #3259 from YosysHQ/micko/verific_valgrind

Fix valgrind tests when using verific
This commit is contained in:
Miodrag Milanović 2022-03-30 17:29:40 +02:00 committed by GitHub
commit 18fb73fd89
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5 changed files with 16 additions and 8 deletions

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@ -2239,11 +2239,15 @@ void verific_import(Design *design, const std::map<std::string,std::string> &par
nl_todo.erase(it); nl_todo.erase(it);
} }
hier_tree::DeleteHierarchicalTree();
veri_file::Reset(); veri_file::Reset();
#ifdef VERIFIC_VHDL_SUPPORT #ifdef VERIFIC_VHDL_SUPPORT
vhdl_file::Reset(); vhdl_file::Reset();
#endif #endif
Libset::Reset(); Libset::Reset();
Message::Reset();
RuntimeFlags::DeleteAllFlags();
LineFile::DeleteAllLineFiles();
verific_incdirs.clear(); verific_incdirs.clear();
verific_libdirs.clear(); verific_libdirs.clear();
verific_import_pending = false; verific_import_pending = false;
@ -3248,11 +3252,15 @@ struct VerificPass : public Pass {
nl_todo.erase(it); nl_todo.erase(it);
} }
hier_tree::DeleteHierarchicalTree();
veri_file::Reset(); veri_file::Reset();
#ifdef VERIFIC_VHDL_SUPPORT #ifdef VERIFIC_VHDL_SUPPORT
vhdl_file::Reset(); vhdl_file::Reset();
#endif #endif
Libset::Reset(); Libset::Reset();
Message::Reset();
RuntimeFlags::DeleteAllFlags();
LineFile::DeleteAllLineFiles();
verific_incdirs.clear(); verific_incdirs.clear();
verific_libdirs.clear(); verific_libdirs.clear();
verific_import_pending = false; verific_import_pending = false;

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@ -1,6 +1,6 @@
`default_nettype none `default_nettype none
module hierdefparam_top(input [7:0] A, output [7:0] Y); module hierdefparam_top(input wire [7:0] A, output wire [7:0] Y);
generate begin:foo generate begin:foo
hierdefparam_a mod_a(.A(A), .Y(Y)); hierdefparam_a mod_a(.A(A), .Y(Y));
end endgenerate end endgenerate
@ -8,7 +8,7 @@ module hierdefparam_top(input [7:0] A, output [7:0] Y);
defparam foo.mod_a.bar[1].mod_b.addvalue = 43; defparam foo.mod_a.bar[1].mod_b.addvalue = 43;
endmodule endmodule
module hierdefparam_a(input [7:0] A, output [7:0] Y); module hierdefparam_a(input wire [7:0] A, output wire [7:0] Y);
genvar i; genvar i;
generate generate
for (i = 0; i < 2; i=i+1) begin:bar for (i = 0; i < 2; i=i+1) begin:bar
@ -19,7 +19,7 @@ module hierdefparam_a(input [7:0] A, output [7:0] Y);
assign bar[0].a = A, bar[1].a = bar[0].y, Y = bar[1].y; assign bar[0].a = A, bar[1].a = bar[0].y, Y = bar[1].y;
endmodule endmodule
module hierdefparam_b(input [7:0] A, output [7:0] Y); module hierdefparam_b(input wire [7:0] A, output wire [7:0] Y);
parameter [7:0] addvalue = 44; parameter [7:0] addvalue = 44;
assign Y = A + addvalue; assign Y = A + addvalue;
endmodule endmodule

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@ -3,7 +3,7 @@
module module_scope_Example(o1, o2); module module_scope_Example(o1, o2);
parameter [31:0] v1 = 10; parameter [31:0] v1 = 10;
parameter [31:0] v2 = 20; parameter [31:0] v2 = 20;
output [31:0] o1, o2; output wire [31:0] o1, o2;
assign module_scope_Example.o1 = module_scope_Example.v1; assign module_scope_Example.o1 = module_scope_Example.v1;
assign module_scope_Example.o2 = module_scope_Example.v2; assign module_scope_Example.o2 = module_scope_Example.v2;
endmodule endmodule
@ -11,14 +11,14 @@ endmodule
module module_scope_ExampleLong(o1, o2); module module_scope_ExampleLong(o1, o2);
parameter [31:0] ThisIsAnExtremelyLongParameterNameToTriggerTheSHA1Checksum1 = 10; parameter [31:0] ThisIsAnExtremelyLongParameterNameToTriggerTheSHA1Checksum1 = 10;
parameter [31:0] ThisIsAnExtremelyLongParameterNameToTriggerTheSHA1Checksum2 = 20; parameter [31:0] ThisIsAnExtremelyLongParameterNameToTriggerTheSHA1Checksum2 = 20;
output [31:0] o1, o2; output wire [31:0] o1, o2;
assign module_scope_ExampleLong.o1 = module_scope_ExampleLong.ThisIsAnExtremelyLongParameterNameToTriggerTheSHA1Checksum1; assign module_scope_ExampleLong.o1 = module_scope_ExampleLong.ThisIsAnExtremelyLongParameterNameToTriggerTheSHA1Checksum1;
assign module_scope_ExampleLong.o2 = module_scope_ExampleLong.ThisIsAnExtremelyLongParameterNameToTriggerTheSHA1Checksum2; assign module_scope_ExampleLong.o2 = module_scope_ExampleLong.ThisIsAnExtremelyLongParameterNameToTriggerTheSHA1Checksum2;
endmodule endmodule
module module_scope_top( module module_scope_top(
output [31:0] a1, a2, b1, b2, c1, c2, output wire [31:0] a1, a2, b1, b2, c1, c2,
output [31:0] d1, d2, e1, e2, f1, f2 output wire [31:0] d1, d2, e1, e2, f1, f2
); );
module_scope_Example a(a1, a2); module_scope_Example a(a1, a2);
module_scope_Example #(1) b(b1, b2); module_scope_Example #(1) b(b1, b2);

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@ -1,4 +1,4 @@
module test_specify; module test_specify(input A, output B);
specparam a=1; specparam a=1;