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Output has priority over input when stitching in abc9

This commit is contained in:
Eddie Hung 2019-08-29 17:24:03 -07:00
parent c52db44f9a
commit 18cabe9370
1 changed files with 10 additions and 13 deletions
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23
passes/techmap/abc9.cc
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@ -694,30 +694,27 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
int in_wires = 0, out_wires = 0; int in_wires = 0, out_wires = 0;
// Stitch in mapped_mod's inputs/outputs into module // Stitch in mapped_mod's inputs/outputs into module
for (auto &it : mapped_mod->wires_) { for (auto port : mapped_mod->ports) {
RTLIL::Wire *w = it.second; RTLIL::Wire *w = mapped_mod->wire(port);
if (!w->port_input && !w->port_output) RTLIL::Wire *wire = module->wire(port);
continue;
RTLIL::Wire *wire = module->wire(w->name);
log_assert(wire); log_assert(wire);
RTLIL::Wire *remap_wire = module->wire(remap_name(w->name)); RTLIL::Wire *remap_wire = module->wire(remap_name(port));
RTLIL::SigSpec signal = RTLIL::SigSpec(wire, 0, GetSize(remap_wire)); RTLIL::SigSpec signal = RTLIL::SigSpec(wire, 0, GetSize(remap_wire));
log_assert(GetSize(signal) >= GetSize(remap_wire)); log_assert(GetSize(signal) >= GetSize(remap_wire));
log_assert(w->port_input || w->port_output);
RTLIL::SigSig conn; RTLIL::SigSig conn;
if (w->port_input) {
conn.first = remap_wire;
conn.second = signal;
in_wires++;
module->connect(conn);
}
if (w->port_output) { if (w->port_output) {
conn.first = signal; conn.first = signal;
conn.second = remap_wire; conn.second = remap_wire;
out_wires++; out_wires++;
module->connect(conn); module->connect(conn);
} }
else if (w->port_input) {
conn.first = remap_wire;
conn.second = signal;
in_wires++;
module->connect(conn);
}
} }
for (auto &it : bit_users) for (auto &it : bit_users)