mirror of https://github.com/YosysHQ/yosys.git
xilinx_srl to use 'slice' features of pmgen for word level
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parent
f4fd41d5d2
commit
18b64609c2
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@ -105,13 +105,15 @@ void run_variable(xilinx_srl_pm &pm)
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log("Found variable chain of length %d (%s):\n", GetSize(ud.chain), log_id(st.first->type));
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log("Found variable chain of length %d (%s):\n", GetSize(ud.chain), log_id(st.first->type));
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auto last_cell = ud.chain.back();
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auto last_cell = ud.chain.back().first;
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SigSpec initval;
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SigSpec initval;
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for (auto cell : ud.chain) {
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for (const auto &i : ud.chain) {
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auto cell = i.first;
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auto slice = i.second;
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log_debug(" %s\n", log_id(cell));
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log_debug(" %s\n", log_id(cell));
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if (cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_))) {
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if (cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_), ID($dff), ID($dffe))) {
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SigBit Q = cell->getPort(ID(Q));
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SigBit Q = cell->getPort(ID(Q))[slice];
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log_assert(Q.wire);
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log_assert(Q.wire);
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auto it = Q.wire->attributes.find(ID(init));
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auto it = Q.wire->attributes.find(ID(init));
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if (it != Q.wire->attributes.end()) {
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if (it != Q.wire->attributes.end()) {
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@ -123,7 +125,7 @@ void run_variable(xilinx_srl_pm &pm)
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else
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else
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log_abort();
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log_abort();
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if (cell != last_cell)
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if (cell != last_cell)
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pm.autoremove(cell);
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cell->connections_.at(ID(Q))[slice] = pm.module->addWire(NEW_ID);
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}
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}
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pm.autoremove(st.shiftx);
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pm.autoremove(st.shiftx);
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@ -131,23 +133,36 @@ void run_variable(xilinx_srl_pm &pm)
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SigBit Q = st.first->getPort(ID(Q));
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SigBit Q = st.first->getPort(ID(Q));
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c->setPort(ID(Q), Q);
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c->setPort(ID(Q), Q);
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if (c->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_))) {
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if (c->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_), ID($dff), ID($dffe))) {
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c->parameters.clear();
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Const clkpol, enpol;
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c->setParam(ID(DEPTH), GetSize(ud.chain));
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c->setParam(ID(INIT), initval.as_const());
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if (c->type.in(ID($_DFF_P_), ID($_DFFE_PN_), ID($_DFFE_PP_)))
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if (c->type.in(ID($_DFF_P_), ID($_DFFE_PN_), ID($_DFFE_PP_)))
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c->setParam(ID(CLKPOL), 1);
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clkpol = 1;
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else if (c->type.in(ID($_DFF_N_), ID($DFFE_NN_), ID($_DFFE_NP_), ID(FDRE_1)))
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else if (c->type.in(ID($_DFF_N_), ID($DFFE_NN_), ID($_DFFE_NP_)))
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c->setParam(ID(CLKPOL), 0);
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clkpol = 0;
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else if (c->type.in(ID($dff), ID($dffe))) {
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clkpol = c->getParam(ID(CLK_POLARITY));
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c->setPort(ID(C), c->getPort(ID(CLK)));
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c->unsetPort(ID(CLK));
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}
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else
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else
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log_abort();
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log_abort();
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if (c->type.in(ID($_DFFE_NP_), ID($_DFFE_PP_)))
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if (c->type.in(ID($_DFFE_NP_), ID($_DFFE_PP_)))
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c->setParam(ID(ENPOL), 1);
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enpol = 1;
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else if (c->type.in(ID($_DFFE_NN_), ID($_DFFE_PN_)))
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else if (c->type.in(ID($_DFFE_NN_), ID($_DFFE_PN_)))
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c->setParam(ID(ENPOL), 0);
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enpol = 0;
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else if (c->type.in(ID($dffe))) {
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enpol = c->getParam(ID(EN_POLARITY));
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c->setPort(ID(E), c->getPort(ID(EN)));
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c->unsetPort(ID(EN));
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}
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else
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else
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c->setParam(ID(ENPOL), 2);
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enpol = 2;
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if (c->type.in(ID($_DFF_N_), ID($_DFF_P_)))
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c->parameters.clear();
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c->setParam(ID(DEPTH), GetSize(ud.chain));
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c->setParam(ID(INIT), initval.as_const());
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c->setParam(ID(CLKPOL), clkpol);
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c->setParam(ID(ENPOL), enpol);
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if (c->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($dff)))
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c->setPort(ID(E), State::S1);
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c->setPort(ID(E), State::S1);
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c->setPort(ID(L), st.shiftx->getPort(ID(B)));
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c->setPort(ID(L), st.shiftx->getPort(ID(B)));
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c->setPort(ID(Q), st.shiftx->getPort(ID(Y)));
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c->setPort(ID(Q), st.shiftx->getPort(ID(Y)));
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@ -151,8 +151,9 @@ endcode
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pattern variable
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pattern variable
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state <int> shiftx_width
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state <int> shiftx_width
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state <int> slice
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udata <int> minlen
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udata <int> minlen
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udata <vector<Cell*>> chain
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udata <vector<pair<Cell*,int>>> chain
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match shiftx
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match shiftx
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select shiftx->type.in($shiftx)
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select shiftx->type.in($shiftx)
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@ -166,13 +167,16 @@ code shiftx_width
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endcode
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endcode
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match first
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match first
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select first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_)
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select first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, $dff, $dffe)
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select nusers(port(first, \Q)) == 2
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select !first->has_keep_attr()
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index <SigBit> port(first, \Q) === port(shiftx, \A)[shiftx_width-1]
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slice idx GetSize(port(first, \Q))
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select nusers(port(first, \Q)[idx]) == 2
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index <SigBit> port(first, \Q)[idx] === port(shiftx, \A)[shiftx_width-1]
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set slice idx
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endmatch
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endmatch
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code
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code
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chain.push_back(first);
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chain.emplace_back(first, slice);
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subpattern(tail);
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subpattern(tail);
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finally
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finally
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if (GetSize(chain) == shiftx_width)
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if (GetSize(chain) == shiftx_width)
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@ -185,26 +189,24 @@ endcode
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subpattern tail
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subpattern tail
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arg shiftx
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arg shiftx
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arg shiftx_width
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arg shiftx_width
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arg slice
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match next
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match next
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semioptional
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semioptional
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select next->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_)
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select next->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, $dff, $dffe)
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select !next->has_keep_attr()
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select !next->has_keep_attr()
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select !port(next, \D)[0].wire->get_bool_attribute(\keep)
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select !port(next, \D)[0].wire->get_bool_attribute(\keep)
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select nusers(port(next, \Q)) == 3
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slice idx GetSize(port(next, \Q))
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index <IdString> next->type === chain.back()->type
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select nusers(port(next, \Q)[idx]) == 3
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index <SigBit> port(next, \Q) === port(chain.back(), \D)
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index <IdString> next->type === chain.back().first->type
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index <SigBit> port(next, \Q) === port(shiftx, \A)[shiftx_width-1-GetSize(chain)]
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index <SigBit> port(next, \Q)[idx] === port(chain.back().first, \D)[chain.back().second]
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index <SigBit> port(next, \Q)[idx] === port(shiftx, \A)[shiftx_width-1-GetSize(chain)]
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set slice idx
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endmatch
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endmatch
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code
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code
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if (next) {
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if (next) {
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auto sig = port(next, \Q);
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chain.emplace_back(next, slice);
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log_warning("nusers of '%s'\n", log_signal(sig));
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for (auto bit : sigmap(sig))
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for (auto user : sigusers[bit])
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log_warning("\t%s\n", log_id(user));
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chain.push_back(next);
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if (GetSize(chain) < shiftx_width)
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if (GetSize(chain) < shiftx_width)
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subpattern(tail);
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subpattern(tail);
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}
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}
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