mirror of https://github.com/YosysHQ/yosys.git
Add dffunmap pass.
To be used with backends that cannot deal with fancy FF types (like blif or smt).
This commit is contained in:
Marcelina Kościelnicka
parent
6cd135a5eb
commit
18ad56ef41
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@ -43,6 +43,7 @@ OBJS += passes/techmap/attrmap.o
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OBJS += passes/techmap/zinit.o
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OBJS += passes/techmap/dfflegalize.o
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OBJS += passes/techmap/dff2dffs.o
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OBJS += passes/techmap/dffunmap.o
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OBJS += passes/techmap/flowmap.o
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OBJS += passes/techmap/extractinv.o
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endif
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@ -0,0 +1,107 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2020 Marcelina Kościelnicka <mwk@0x04.net>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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#include "kernel/ff.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct DffunmapPass : public Pass {
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DffunmapPass() : Pass("dffunmap", "unmap clock enable and synchronous reset from FFs") { }
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" dffunmap [options] [selection]\n");
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log("\n");
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log("This pass transforms FF types with clock enable and/or synchronous reset into\n");
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log("their base type (with neither clock enable nor sync reset) by emulating the clock\n");
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log("enable and synchronous reset with multiplexers on the cell input.\n");
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log("\n");
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log(" -ce-only\n");
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log(" unmap only clock enables, leave synchronous resets alone.\n");
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log("\n");
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log(" -srst-only\n");
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log(" unmap only synchronous resets, leave clock enables alone.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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log_header(design, "Executing DFFUNMAP pass (unmap clock enable and synchronous reset from FFs).\n");
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bool ce_only = false;
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bool srst_only = false;
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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if (args[argidx] == "-ce-only") {
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ce_only = true;
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continue;
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}
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if (args[argidx] == "-srst-only") {
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srst_only = true;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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if (ce_only && srst_only)
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log_cmd_error("Options -ce-only and -srst-only are mutually exclusive!\n");
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for (auto mod : design->selected_modules())
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{
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SigMap sigmap(mod);
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FfInitVals initvals(&sigmap, mod);
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for (auto cell : mod->selected_cells())
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{
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if (!RTLIL::builtin_ff_cell_types().count(cell->type))
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continue;
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FfData ff(&initvals, cell);
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IdString name = cell->name;
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if (!ff.has_clk)
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continue;
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if (ce_only) {
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if (!ff.has_en)
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continue;
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ff.unmap_ce(mod);
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} else if (srst_only) {
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if (!ff.has_srst)
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continue;
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ff.unmap_srst(mod);
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} else {
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if (!ff.has_en && !ff.has_srst)
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continue;
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ff.unmap_ce_srst(mod);
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}
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mod->remove(cell);
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ff.emit(mod, name);
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}
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}
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}
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} DffunmapPass;
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PRIVATE_NAMESPACE_END
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@ -0,0 +1,100 @@
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read_verilog -icells << EOT
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module top(...);
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input C, R, E, S;
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input [1:0] D;
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output [20:0] Q;
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$dff #(.CLK_POLARITY(1'b0), .WIDTH(2)) ff0 (.CLK(C), .D(D), .Q(Q[1:0]));
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$dffe #(.CLK_POLARITY(1'b0), .EN_POLARITY(1'b0), .WIDTH(2)) ff1 (.CLK(C), .EN(E), .D(D), .Q(Q[3:2]));
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$sdff #(.CLK_POLARITY(1'b0), .WIDTH(2), .SRST_POLARITY(1'b0), .SRST_VALUE(2'h2)) ff2 (.CLK(C), .SRST(R), .D(D), .Q(Q[5:4]));
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$sdffe #(.CLK_POLARITY(1'b0), .EN_POLARITY(1'b1), .WIDTH(2), .SRST_POLARITY(1'b1), .SRST_VALUE(2'h2)) ff3 (.CLK(C), .EN(E), .SRST(R), .D(D), .Q(Q[7:6]));
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$sdffce #(.CLK_POLARITY(1'b0), .EN_POLARITY(1'b1), .WIDTH(2), .SRST_POLARITY(1'b1), .SRST_VALUE(2'h2)) ff4 (.CLK(C), .EN(E), .SRST(R), .D(D), .Q(Q[9:8]));
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$adff #(.CLK_POLARITY(1'b0), .WIDTH(2), .ARST_POLARITY(1'b0), .ARST_VALUE(2'h2)) ff5 (.CLK(C), .ARST(R), .D(D), .Q(Q[11:10]));
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$adffe #(.CLK_POLARITY(1'b0), .EN_POLARITY(1'b1), .WIDTH(2), .ARST_POLARITY(1'b1), .ARST_VALUE(2'h2)) ff6 (.CLK(C), .EN(E), .ARST(R), .D(D), .Q(Q[13:12]));
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$dffsr #(.CLK_POLARITY(1'b0), .WIDTH(2), .CLR_POLARITY(1'b0), .SET_POLARITY(1'b1)) ff7 (.CLK(C), .CLR({R, S}), .SET({S, R}), .D(D), .Q(Q[15:14]));
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$dffsre #(.CLK_POLARITY(1'b0), .EN_POLARITY(1'b1), .WIDTH(2), .CLR_POLARITY(1'b1), .SET_POLARITY(1'b0)) ff8 (.CLK(C), .EN(E), .CLR({R, R}), .SET({S, S}), .D(D), .Q(Q[17:16]));
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endmodule
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EOT
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design -save orig
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equiv_opt -assert -async2sync dffunmap
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design -load postopt
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select -assert-none t:$sdff t:$dffe t:$adffe t:$sdffe t:$sdffce t:$dffsre
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select -assert-count 5 t:$dff
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select -assert-count 2 t:$adff
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select -assert-count 2 t:$dffsr
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design -load orig
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equiv_opt -assert -async2sync dffunmap -ce-only
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design -load postopt
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select -assert-none t:$dffe t:$adffe t:$sdffe t:$sdffce t:$dffsre
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select -assert-count 3 t:$dff
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select -assert-count 2 t:$sdff
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select -assert-count 2 t:$adff
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select -assert-count 2 t:$dffsr
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design -load orig
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equiv_opt -assert -async2sync dffunmap -srst-only
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design -load postopt
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select -assert-none t:$sdff t:$sdffe t:$sdffce
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select -assert-count 3 t:$dff
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select -assert-count 2 t:$dffe
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select -assert-count 1 t:$adff
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select -assert-count 1 t:$adffe
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select -assert-count 1 t:$dffsr
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select -assert-count 1 t:$dffsre
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design -load orig
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simplemap
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equiv_opt -assert -async2sync dffunmap
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design -load postopt
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select -assert-none t:$_SDFF* t:$_DFFE_* t:$_DFFSRE_*
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select -assert-count 10 t:$_DFF_N_
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select -assert-count 1 t:$_DFF_NP0_
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select -assert-count 1 t:$_DFF_NN0_
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select -assert-count 1 t:$_DFF_NP1_
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select -assert-count 1 t:$_DFF_NN1_
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select -assert-count 2 t:$_DFFSR_NPN_
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select -assert-count 2 t:$_DFFSR_NNP_
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design -load orig
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simplemap
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equiv_opt -assert -async2sync dffunmap -ce-only
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design -load postopt
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select -assert-none t:$_SDFFE_* t:$_SDFFCE_* t:$_DFFE_* t:$_DFFSRE_*
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select -assert-count 6 t:$_DFF_N_
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select -assert-count 1 t:$_SDFF_NP0_
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select -assert-count 1 t:$_SDFF_NN0_
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select -assert-count 1 t:$_SDFF_NP1_
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select -assert-count 1 t:$_SDFF_NN1_
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select -assert-count 1 t:$_DFF_NP0_
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select -assert-count 1 t:$_DFF_NN0_
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select -assert-count 1 t:$_DFF_NP1_
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select -assert-count 1 t:$_DFF_NN1_
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select -assert-count 2 t:$_DFFSR_NPN_
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select -assert-count 2 t:$_DFFSR_NNP_
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design -load orig
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simplemap
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equiv_opt -assert -async2sync dffunmap -srst-only
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design -load postopt
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select -assert-none t:$sdff t:$sdffe t:$sdffce
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select -assert-count 6 t:$_DFF_N_
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select -assert-count 2 t:$_DFFE_NP_
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select -assert-count 2 t:$_DFFE_NN_
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select -assert-count 1 t:$_DFF_NN0_
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select -assert-count 1 t:$_DFF_NN1_
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select -assert-count 1 t:$_DFFE_NP0P_
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select -assert-count 1 t:$_DFFE_NP1P_
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select -assert-count 2 t:$_DFFSR_NPN_
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select -assert-count 2 t:$_DFFSRE_NNPP_
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