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Merge pull request #4211 from jix/fix-check-clk2fflogic 

clk2fflogic: Fix handling of $check cells
This commit is contained in:
Martin Povišer 2024-02-14 13:05:39 +01:00 committed by GitHub
parent 91685355a0 bbdfcfdf30
commit 18a5989084
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GPG Key ID: B5690EEEBB952194
3 changed files with 43 additions and 15 deletions
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3
passes/sat/clk2fflogic.cc
View File

@ -238,7 +238,8 @@ struct Clk2fflogicPass : public Pass {
cell->setPort(ID::EN, module->And(NEW_ID, sig_en_sampled, sig_trg_combined));
cell->setPort(ID::ARGS, sig_args_sampled);
if (cell->type == ID($check)) {
SigBit sig_a_sampled = sample_data(module, sig_en, State::S1, false, false).sampled;
SigBit sig_a = cell->getPort(ID::A);
SigBit sig_a_sampled = sample_data(module, sig_a, State::S1, false, false).sampled;
cell->setPort(ID::A, sig_a_sampled);
}
}

32
tests/various/clk2fflogic_effects.sh
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@ -1,27 +1,35 @@
#!/usr/bin/env bash
set -ex
set -e
../../yosys -p "
read_verilog -formal -DFAST clk2fflogic_effects.sv
# TODO: when sim gets native $check support, remove the -DNO_ASSERT here
echo Running yosys sim
../../yosys -q -p "
read_verilog -formal -DNO_ASSERT clk2fflogic_effects.sv
hierarchy -top top; proc;;
tee -o clk2fflogic_effects.sim.log sim -fst clk2fflogic_effects.sim.fst -q -n 16
"
../../yosys -p "
read_verilog -formal -DFAST clk2fflogic_effects.sv
tee -q -o clk2fflogic_effects.sim.log sim -q -n 32
"
echo Running yosys clk2fflogic sim
../../yosys -q -p "
read_verilog -formal clk2fflogic_effects.sv
hierarchy -top top; proc;;
clk2fflogic;;
tee -o clk2fflogic_effects.clk2fflogic.log sim -fst clk2fflogic_effects.clk2fflogic.fst -q -n 16
logger -nowarn ^Assertion
tee -q -o clk2fflogic_effects.clk2fflogic.log sim -q -n 32
"
iverilog -g2012 -o clk2fflogic_effects.iv.out clk2fflogic_effects.sv
echo Running iverilog sim
iverilog -g2012 -DNO_ASSERT -o clk2fflogic_effects.iv.out clk2fflogic_effects.sv
./clk2fflogic_effects.iv.out > clk2fflogic_effects.iv.log
sort clk2fflogic_effects.iv.log > clk2fflogic_effects.iv.sorted.log
tail -n +3 clk2fflogic_effects.sim.log | sort > clk2fflogic_effects.sim.sorted.log
tail -n +3 clk2fflogic_effects.clk2fflogic.log | sort > clk2fflogic_effects.clk2fflogic.sorted.log
gawk '/([0-9]+):/{T=$1;print};/^Failed/{print T,$0}' clk2fflogic_effects.iv.log | sort > clk2fflogic_effects.iv.sorted.log
gawk '/([0-9]+):/{T=$1;print};/^Failed/{print T,$0}' clk2fflogic_effects.sim.log | sort > clk2fflogic_effects.sim.sorted.log
gawk '/([0-9]+):/{T=$1;print};/^Failed/{print T,$0}' clk2fflogic_effects.clk2fflogic.log | sort > clk2fflogic_effects.clk2fflogic.sorted.log
echo Comparing iverilog sim vs yosys sim
cmp clk2fflogic_effects.iv.sorted.log clk2fflogic_effects.sim.sorted.log
echo Comparing iverilog sim vs yosys clk2fflogic sim
cmp clk2fflogic_effects.iv.sorted.log clk2fflogic_effects.clk2fflogic.sorted.log

23
tests/various/clk2fflogic_effects.sv
View File

@ -7,7 +7,7 @@ reg clk = 0;
always @(posedge gclk)
clk <= !clk;
reg [4:0] counter = 0;
reg [5:0] counter = 0;
reg eff_0_trg = '0;
reg eff_0_en = '0;
@ -20,6 +20,10 @@ reg eff_2_trgA = '0;
reg eff_2_trgB = '0;
reg eff_2_en = '0;
reg eff_3_trg = '0;
reg eff_3_en = '0;
reg eff_3_a = '0;
`ifdef FAST
always @(posedge gclk) begin
`else
@ -37,6 +41,10 @@ always @(posedge clk) begin
eff_2_trgA = counter[0];
eff_2_trgB = !counter[0];
eff_2_en <= 32'b00000000000000000000001111111100 >> counter;
eff_3_trg = 32'b10101010101010101010101010101010 >> counter;
eff_3_en <= 32'b11101110010001001110111001000100 >> counter;
eff_3_a <= 32'b11111010111110100101000001010000 >> counter;
end
always @(posedge eff_0_trg)
@ -71,11 +79,22 @@ always @(posedge eff_2_trgA, posedge eff_2_trgB)
if (eff_2_en)
$display("repeated");
always @(posedge eff_3_trg)
if (eff_3_en) begin
$display("%02d: eff3 vvv", counter);
`ifdef NO_ASSERT
if (!eff_3_a)
$display("Failed assertion eff3 at");
`else
eff3: assert(eff_3_a);
`endif
end
`ifdef __ICARUS__
initial gclk = 0;
always @(gclk) gclk <= #5 !gclk;
always @(posedge gclk)
if (counter == 31)
if (counter == 32)
$finish(0);
`endif