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Merge pull request #936 from YosysHQ/README-fix-quotes 

README: fix some incorrect quoting
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Eddie Hung 2019-04-15 12:22:05 -07:00 committed by GitHub
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@ -312,10 +312,10 @@ Verilog Attributes and non-standard features
passes to identify input and output ports of cells. The Verilog backend passes to identify input and output ports of cells. The Verilog backend
also does not output blackbox modules on default. also does not output blackbox modules on default.
- The ``dynports'' attribute is used by the Verilog front-end to mark modules - The ``dynports`` attribute is used by the Verilog front-end to mark modules
that have ports with a width that depends on a parameter. that have ports with a width that depends on a parameter.
- The ``hdlname'' attribute is used by some passes to document the original - The ``hdlname`` attribute is used by some passes to document the original
(HDL) name of a module when renaming a module. (HDL) name of a module when renaming a module.
- The ``keep`` attribute on cells and wires is used to mark objects that should - The ``keep`` attribute on cells and wires is used to mark objects that should