From b5c15636c5594c2ea2f5b73919edf66d3e2478e7 Mon Sep 17 00:00:00 2001 From: Andrew Zonenberg Date: Mon, 28 Aug 2017 20:52:08 -0700 Subject: [PATCH 1/5] Refactoring: Renamed greenpak4_counters pass to extract_counter, moved it to techmap/ since it's going to become a generic pass --- passes/techmap/Makefile.inc | 1 + .../techmap/extract_counter.cc | 22 +++++++++---------- techlibs/greenpak4/Makefile.inc | 1 - techlibs/greenpak4/synth_greenpak4.cc | 2 +- 4 files changed, 13 insertions(+), 13 deletions(-) rename techlibs/greenpak4/greenpak4_counters.cc => passes/techmap/extract_counter.cc (95%) diff --git a/passes/techmap/Makefile.inc b/passes/techmap/Makefile.inc index 3f8a6feb5..140a9f892 100644 --- a/passes/techmap/Makefile.inc +++ b/passes/techmap/Makefile.inc @@ -17,6 +17,7 @@ OBJS += passes/techmap/iopadmap.o OBJS += passes/techmap/hilomap.o OBJS += passes/techmap/extract.o OBJS += passes/techmap/extract_fa.o +OBJS += passes/techmap/extract_counter.o OBJS += passes/techmap/extract_reduce.o OBJS += passes/techmap/alumacc.o OBJS += passes/techmap/dff2dffe.o diff --git a/techlibs/greenpak4/greenpak4_counters.cc b/passes/techmap/extract_counter.cc similarity index 95% rename from techlibs/greenpak4/greenpak4_counters.cc rename to passes/techmap/extract_counter.cc index 50a237b1b..54584b6f3 100644 --- a/techlibs/greenpak4/greenpak4_counters.cc +++ b/passes/techmap/extract_counter.cc @@ -103,7 +103,7 @@ struct CounterExtraction }; //attempt to extract a counter centered on the given adder cell -int greenpak4_counters_tryextract(ModIndex& index, Cell *cell, CounterExtraction& extract) +int counter_tryextract(ModIndex& index, Cell *cell, CounterExtraction& extract) { SigMap& sigmap = index.sigmap; @@ -276,7 +276,7 @@ int greenpak4_counters_tryextract(ModIndex& index, Cell *cell, CounterExtraction return 0; } -void greenpak4_counters_worker( +void counter_worker( ModIndex& index, Cell *cell, unsigned int& total_counters, @@ -328,7 +328,7 @@ void greenpak4_counters_worker( //Attempt to extract a counter CounterExtraction extract; - int reason = greenpak4_counters_tryextract(index, cell, extract); + int reason = counter_tryextract(index, cell, extract); //Nonzero code - we could not find a matchable counter. //Do nothing, unless extraction was forced in which case give an error @@ -455,21 +455,21 @@ void greenpak4_counters_worker( cells_to_rename.insert(pair(cell, countname)); } -struct Greenpak4CountersPass : public Pass { - Greenpak4CountersPass() : Pass("greenpak4_counters", "Extract GreenPak4 counter cells") { } +struct ExtractCounterPass : public Pass { + ExtractCounterPass() : Pass("extract_counter", "Extract GreenPak4 counter cells") { } virtual void help() { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); - log(" greenpak4_counters [options] [selection]\n"); + log(" extract_counter [options] [selection]\n"); log("\n"); - log("This pass converts non-resettable or async resettable down counters to GreenPak4\n"); - log("counter cells (All other GreenPak4 counter modes must be instantiated manually.)\n"); + log("This pass converts non-resettable or async resettable down counters to\n"); + log("counter cells\n"); log("\n"); } virtual void execute(std::vector args, RTLIL::Design *design) { - log_header(design, "Executing GREENPAK4_COUNTERS pass (mapping counters to hard IP blocks).\n"); + log_header(design, "Executing EXTRACT_COUNTER pass (find counters in netlist).\n"); size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) @@ -490,7 +490,7 @@ struct Greenpak4CountersPass : public Pass { ModIndex index(module); for (auto cell : module->selected_cells()) - greenpak4_counters_worker(index, cell, total_counters, cells_to_remove, cells_to_rename); + counter_worker(index, cell, total_counters, cells_to_remove, cells_to_rename); for(auto cell : cells_to_remove) { @@ -508,6 +508,6 @@ struct Greenpak4CountersPass : public Pass { if(total_counters) log("Extracted %u counters\n", total_counters); } -} Greenpak4CountersPass; +} ExtractCounterPass; PRIVATE_NAMESPACE_END diff --git a/techlibs/greenpak4/Makefile.inc b/techlibs/greenpak4/Makefile.inc index f9614e779..1169b23cf 100644 --- a/techlibs/greenpak4/Makefile.inc +++ b/techlibs/greenpak4/Makefile.inc @@ -1,6 +1,5 @@ OBJS += techlibs/greenpak4/synth_greenpak4.o -OBJS += techlibs/greenpak4/greenpak4_counters.o OBJS += techlibs/greenpak4/greenpak4_dffinv.o $(eval $(call add_share_file,share/greenpak4,techlibs/greenpak4/cells_latch.v)) diff --git a/techlibs/greenpak4/synth_greenpak4.cc b/techlibs/greenpak4/synth_greenpak4.cc index 92bcc8de7..1fb99c348 100644 --- a/techlibs/greenpak4/synth_greenpak4.cc +++ b/techlibs/greenpak4/synth_greenpak4.cc @@ -155,7 +155,7 @@ struct SynthGreenPAK4Pass : public ScriptPass if (check_label("fine")) { - run("greenpak4_counters"); + run("extract_counter"); run("clean"); run("opt -fast -mux_undef -undriven -fine"); run("memory_map"); From 46b01f05bba64a8dc42f0e34f767e7aa44b43a06 Mon Sep 17 00:00:00 2001 From: Andrew Zonenberg Date: Mon, 28 Aug 2017 21:48:20 -0700 Subject: [PATCH 2/5] Refactored extract_counter to be generic vs GreenPAK specific --- passes/techmap/extract_counter.cc | 136 +++++++++++++++++++----------- 1 file changed, 86 insertions(+), 50 deletions(-) diff --git a/passes/techmap/extract_counter.cc b/passes/techmap/extract_counter.cc index 54584b6f3..9f14f5d8b 100644 --- a/passes/techmap/extract_counter.cc +++ b/passes/techmap/extract_counter.cc @@ -103,15 +103,17 @@ struct CounterExtraction }; //attempt to extract a counter centered on the given adder cell -int counter_tryextract(ModIndex& index, Cell *cell, CounterExtraction& extract) +//For now we only support DOWN counters. +//TODO: up/down support +int counter_tryextract(ModIndex& index, Cell *cell, CounterExtraction& extract, pool& parallel_cells) { SigMap& sigmap = index.sigmap; - //GreenPak does not support counters larger than 14 bits so immediately skip anything bigger - //TODO: infer cascaded counters? + //A counter with less than 2 bits makes no sense + //TODO: configurable min/max thresholds int a_width = cell->getParam("\\A_WIDTH").as_int(); extract.width = a_width; - if(a_width > 14) + if(a_width < 2) return 1; //Second input must be a single bit @@ -221,40 +223,43 @@ int counter_tryextract(ModIndex& index, Cell *cell, CounterExtraction& extract) pool cnout_loads = get_other_cells(cnout, index, count_reg); if(cnout_loads.size() > 2) { - //It's OK to have other loads iff they go to a DAC or DCMP (these are POUT) - for(auto c : cnout_loads) + //If we specified a limited set of cells for parallel output, check that we only drive them + if(!parallel_cells.empty()) { - if(c == underflow_inv) - continue; - if(c == cell) - continue; - - //If the cell is not a DAC or DCMP, complain - if( (c->type != "\\GP_DCMP") && (c->type != "\\GP_DAC") ) - return 17; - - //Figure out what port(s) are driven by it - //TODO: this can probably be done more efficiently w/o multiple iterations over our whole net? - RTLIL::IdString portname; - for(auto b : qport) + for(auto c : cnout_loads) { - pool ports = index.query_ports(b); - for(auto x : ports) + if(c == underflow_inv) + continue; + if(c == cell) + continue; + + //Make sure we're in the whitelist + if( parallel_cells.find(c->type) == parallel_cells.end()) + return 17; + + //Figure out what port(s) are driven by it + //TODO: this can probably be done more efficiently w/o multiple iterations over our whole net? + RTLIL::IdString portname; + for(auto b : qport) { - if(x.cell != c) - continue; - if(portname == "") - portname = x.port; + pool ports = index.query_ports(b); + for(auto x : ports) + { + if(x.cell != c) + continue; + if(portname == "") + portname = x.port; - //somehow our counter output is going to multiple ports - //this makes no sense, don't allow inference - else if(portname != x.port) - return 17; + //somehow our counter output is going to multiple ports + //this makes no sense, don't allow inference + else if(portname != x.port) + return 17; + } } - } - //Save the other loads - extract.pouts.insert(ModIndex::PortInfo(c, portname, 0)); + //Save the other loads + extract.pouts.insert(ModIndex::PortInfo(c, portname, 0)); + } } } if(!is_full_bus(cnout, index, count_reg, "\\Q", underflow_inv, "\\A", true)) @@ -281,7 +286,8 @@ void counter_worker( Cell *cell, unsigned int& total_counters, pool& cells_to_remove, - pool>& cells_to_rename) + pool>& cells_to_rename, + pool& parallel_cells) { SigMap& sigmap = index.sigmap; @@ -289,6 +295,8 @@ void counter_worker( if (cell->type != "$alu") return; + log("Looking at cell %s\n", cell->name.c_str()); + //A input is the count value. Check if it has COUNT_EXTRACT set. //If it's not a wire, don't even try auto port = sigmap(cell->getPort("\\A")); @@ -328,7 +336,7 @@ void counter_worker( //Attempt to extract a counter CounterExtraction extract; - int reason = counter_tryextract(index, cell, extract); + int reason = counter_tryextract(index, cell, extract, parallel_cells); //Nonzero code - we could not find a matchable counter. //Do nothing, unless extraction was forced in which case give an error @@ -337,7 +345,7 @@ void counter_worker( static const char* reasons[24]= { "no problem", //0 - "counter is larger than 14 bits", //1 + "counter is too large/small", //1 "counter does not count by one", //2 "counter uses signed math", //3 "counter does not count by one", //4 @@ -353,7 +361,7 @@ void counter_worker( "Mux output is used outside counter", //14 "Counter reg is not DFF/ADFF", //15 "Counter input is not full bus", //16 - "Count register is used outside counter, but not by a DCMP or DAC", //17 + "Count register is used outside counter, but not by an allowed cell", //17 "Register output is not full bus", //18 "Register output is not full bus", //19 "No init value found", //20 @@ -372,13 +380,8 @@ void counter_worker( return; } - //Figure out the final cell type based on the counter size - string celltype = "\\GP_COUNT8"; - if(extract.width > 8) - celltype = "\\GP_COUNT14"; - //Get new cell name - string countname = string("$auto$GP_COUNTx$") + log_id(extract.rwire->name.str()); + string countname = string("$auto$COUNTx$") + log_id(extract.rwire->name.str()); //Log it total_counters ++; @@ -411,7 +414,7 @@ void counter_worker( cell->unsetParam("\\Y_WIDTH"); //Change the cell type - cell->type = celltype; + cell->type = "$__COUNT__"; //Hook up resets if(extract.has_reset) @@ -427,12 +430,19 @@ void counter_worker( } //Hook up other stuff - cell->setParam("\\CLKIN_DIVIDE", RTLIL::Const(1)); + //cell->setParam("\\CLKIN_DIVIDE", RTLIL::Const(1)); cell->setParam("\\COUNT_TO", RTLIL::Const(extract.count_value)); cell->setPort("\\CLK", extract.clk); cell->setPort("\\OUT", extract.outsig); + //Hook up hard-wired ports (for now CE and up/=down are not supported), default to no parallel output + cell->setParam("\\HAS_POUT", RTLIL::Const(0)); + cell->setParam("\\HAS_CE", RTLIL::Const("NO")); + cell->setParam("\\DIRECTION", RTLIL::Const("DOWN")); + cell->setPort("\\CE", RTLIL::Const(1)); + cell->setPort("\\UP", RTLIL::Const(1)); + //Hook up any parallel outputs for(auto load : extract.pouts) { @@ -444,6 +454,7 @@ void counter_worker( //Connect it to our parallel output //(this is OK to do more than once b/c they all go to the same place) cell->setPort("\\POUT", sig); + cell->setParam("\\HAS_POUT", RTLIL::Const(1)); } //Delete the cells we've replaced (let opt_clean handle deleting the now-redundant wires) @@ -464,7 +475,13 @@ struct ExtractCounterPass : public Pass { log(" extract_counter [options] [selection]\n"); log("\n"); log("This pass converts non-resettable or async resettable down counters to\n"); - log("counter cells\n"); + log("counter cells. Use a target-specific 'techmap' map file to convert those cells\n"); + log("to the actual target cells.\n"); + log("\n"); + log(" -pout X,Y,...\n"); + log(" Only allow parallel output from the counter to the listed cell types\n"); + log(" (if not specified, parallel outputs are not restricted)\n"); + log("\n"); log("\n"); } virtual void execute(std::vector args, RTLIL::Design *design) @@ -472,12 +489,31 @@ struct ExtractCounterPass : public Pass { log_header(design, "Executing EXTRACT_COUNTER pass (find counters in netlist).\n"); size_t argidx; + pool parallel_cells; for (argidx = 1; argidx < args.size(); argidx++) { - // if (args[argidx] == "-v") { - // continue; - // } - break; + if (args[argidx] == "-pout") + { + if(argidx + 1 >= args.size()) + { + log_error("extract_counter -pout requires an argument\n"); + return; + } + + std::string pouts = args[++argidx]; + std::string tmp; + for(size_t i=0; iselected_cells()) - counter_worker(index, cell, total_counters, cells_to_remove, cells_to_rename); + counter_worker(index, cell, total_counters, cells_to_remove, cells_to_rename, parallel_cells); for(auto cell : cells_to_remove) { From 3fc1b9f3fdd7f5e8aca25b266cbfea90b519cc42 Mon Sep 17 00:00:00 2001 From: Andrew Zonenberg Date: Mon, 28 Aug 2017 22:13:36 -0700 Subject: [PATCH 3/5] Finished refactoring counter extraction to be nice and generic. Implemented techmapping from $__COUNT_ to GP_COUNTx cells. --- passes/techmap/extract_counter.cc | 36 +++++++++----- techlibs/greenpak4/cells_map.v | 68 +++++++++++++++++++++++++++ techlibs/greenpak4/synth_greenpak4.cc | 2 +- 3 files changed, 94 insertions(+), 12 deletions(-) diff --git a/passes/techmap/extract_counter.cc b/passes/techmap/extract_counter.cc index 9f14f5d8b..c3e7e9400 100644 --- a/passes/techmap/extract_counter.cc +++ b/passes/techmap/extract_counter.cc @@ -105,15 +105,20 @@ struct CounterExtraction //attempt to extract a counter centered on the given adder cell //For now we only support DOWN counters. //TODO: up/down support -int counter_tryextract(ModIndex& index, Cell *cell, CounterExtraction& extract, pool& parallel_cells) +int counter_tryextract( + ModIndex& index, + Cell *cell, + CounterExtraction& extract, + pool& parallel_cells, + int maxwidth) { SigMap& sigmap = index.sigmap; //A counter with less than 2 bits makes no sense - //TODO: configurable min/max thresholds + //TODO: configurable min threshold int a_width = cell->getParam("\\A_WIDTH").as_int(); extract.width = a_width; - if(a_width < 2) + if( (a_width < 2) || (a_width > maxwidth) ) return 1; //Second input must be a single bit @@ -287,7 +292,8 @@ void counter_worker( unsigned int& total_counters, pool& cells_to_remove, pool>& cells_to_rename, - pool& parallel_cells) + pool& parallel_cells, + int maxwidth) { SigMap& sigmap = index.sigmap; @@ -295,8 +301,6 @@ void counter_worker( if (cell->type != "$alu") return; - log("Looking at cell %s\n", cell->name.c_str()); - //A input is the count value. Check if it has COUNT_EXTRACT set. //If it's not a wire, don't even try auto port = sigmap(cell->getPort("\\A")); @@ -336,7 +340,7 @@ void counter_worker( //Attempt to extract a counter CounterExtraction extract; - int reason = counter_tryextract(index, cell, extract, parallel_cells); + int reason = counter_tryextract(index, cell, extract, parallel_cells, maxwidth); //Nonzero code - we could not find a matchable counter. //Do nothing, unless extraction was forced in which case give an error @@ -414,7 +418,7 @@ void counter_worker( cell->unsetParam("\\Y_WIDTH"); //Change the cell type - cell->type = "$__COUNT__"; + cell->type = "$__COUNT_"; //Hook up resets if(extract.has_reset) @@ -432,13 +436,13 @@ void counter_worker( //Hook up other stuff //cell->setParam("\\CLKIN_DIVIDE", RTLIL::Const(1)); cell->setParam("\\COUNT_TO", RTLIL::Const(extract.count_value)); - + cell->setParam("\\WIDTH", RTLIL::Const(extract.width)); cell->setPort("\\CLK", extract.clk); cell->setPort("\\OUT", extract.outsig); //Hook up hard-wired ports (for now CE and up/=down are not supported), default to no parallel output cell->setParam("\\HAS_POUT", RTLIL::Const(0)); - cell->setParam("\\HAS_CE", RTLIL::Const("NO")); + cell->setParam("\\HAS_CE", RTLIL::Const(0)); cell->setParam("\\DIRECTION", RTLIL::Const("DOWN")); cell->setPort("\\CE", RTLIL::Const(1)); cell->setPort("\\UP", RTLIL::Const(1)); @@ -478,6 +482,8 @@ struct ExtractCounterPass : public Pass { log("counter cells. Use a target-specific 'techmap' map file to convert those cells\n"); log("to the actual target cells.\n"); log("\n"); + log(" -maxwidth N\n"); + log(" Only extract counters up to N bits wide\n"); log(" -pout X,Y,...\n"); log(" Only allow parallel output from the counter to the listed cell types\n"); log(" (if not specified, parallel outputs are not restricted)\n"); @@ -488,6 +494,7 @@ struct ExtractCounterPass : public Pass { { log_header(design, "Executing EXTRACT_COUNTER pass (find counters in netlist).\n"); + int maxwidth = 64; size_t argidx; pool parallel_cells; for (argidx = 1; argidx < args.size(); argidx++) @@ -513,6 +520,13 @@ struct ExtractCounterPass : public Pass { tmp += pouts[i]; } parallel_cells.insert(RTLIL::IdString(tmp)); + continue; + } + + if (args[argidx] == "-maxwidth" && argidx+1 < args.size()) + { + maxwidth = atoi(args[++argidx].c_str()); + continue; } } extra_args(args, argidx, design); @@ -526,7 +540,7 @@ struct ExtractCounterPass : public Pass { ModIndex index(module); for (auto cell : module->selected_cells()) - counter_worker(index, cell, total_counters, cells_to_remove, cells_to_rename, parallel_cells); + counter_worker(index, cell, total_counters, cells_to_remove, cells_to_rename, parallel_cells, maxwidth); for(auto cell : cells_to_remove) { diff --git a/techlibs/greenpak4/cells_map.v b/techlibs/greenpak4/cells_map.v index f8fb2569a..1450eac2e 100644 --- a/techlibs/greenpak4/cells_map.v +++ b/techlibs/greenpak4/cells_map.v @@ -144,3 +144,71 @@ module \$lut (A, Y); end endgenerate endmodule + +module \$__COUNT_ (CE, CLK, OUT, POUT, RST, UP); + + input wire CE; + input wire CLK; + output reg OUT; + output reg[WIDTH-1:0] POUT; + input wire RST; + input wire UP; + + parameter COUNT_TO = 1; + parameter RESET_MODE = "RISING"; + parameter HAS_POUT = 0; + parameter HAS_CE = 0; + parameter WIDTH = 8; + parameter DIRECTION = "DOWN"; + + //If we have a CE, or DIRECTION other than DOWN fail... GP_COUNTx_ADV is not supported yet + if(HAS_CE || (DIRECTION != "DOWN") ) begin + initial begin + $display("ERROR: \$__COUNT__ support for GP_COUNTx_ADV is not yet implemented. This counter should never have been extracted (bug in extract_counter pass?)."); + $finish; + end + end + + //If counter is more than 14 bits wide, complain (also shouldn't happen) + else if(WIDTH > 14) begin + initial begin + $display("ERROR: \$__COUNT__ support for cascaded counters is not yet implemented. This counter should never have been extracted (bug in extract_counter pass?)."); + $finish; + end + end + + //If counter is more than 8 bits wide and has parallel output, we have a problem + else if(WIDTH > 8 && HAS_POUT) begin + initial begin + $display("ERROR: \$__COUNT__ support for 9-14 bit counters with parallel output is not yet implemented. This counter should never have been extracted (bug in extract_counter pass?)."); + $finish; + end + end + + //Looks like a legal counter! Do something with it + else if(WIDTH <= 8) begin + GP_COUNT8 #( + .COUNT_TO(COUNT_TO), + .RESET_MODE(RESET_MODE), + .CLKIN_DIVIDE(1) + ) _TECHMAP_REPLACE_ ( + .CLK(CLK), + .RST(RST), + .OUT(OUT), + .POUT(POUT) + ); + end + + else begin + GP_COUNT14 #( + .COUNT_TO(COUNT_TO), + .RESET_MODE(RESET_MODE), + .CLKIN_DIVIDE(1) + ) _TECHMAP_REPLACE_ ( + .CLK(CLK), + .RST(RST), + .OUT(OUT) + ); + end + +endmodule diff --git a/techlibs/greenpak4/synth_greenpak4.cc b/techlibs/greenpak4/synth_greenpak4.cc index 1fb99c348..56ea8003e 100644 --- a/techlibs/greenpak4/synth_greenpak4.cc +++ b/techlibs/greenpak4/synth_greenpak4.cc @@ -155,7 +155,7 @@ struct SynthGreenPAK4Pass : public ScriptPass if (check_label("fine")) { - run("extract_counter"); + run("extract_counter -pout \\GP_DCMP,\\GP_DAC -maxwidth 14"); run("clean"); run("opt -fast -mux_undef -undriven -fine"); run("memory_map"); From 634f18be961683917ca589bed1a44b8031f06764 Mon Sep 17 00:00:00 2001 From: Andrew Zonenberg Date: Wed, 30 Aug 2017 16:27:18 -0700 Subject: [PATCH 4/5] extract_counter: Minor changes requested to comply with upstream policy, fixed a few typos --- passes/techmap/extract_counter.cc | 7 ++++--- techlibs/greenpak4/cells_map.v | 6 +++--- techlibs/greenpak4/synth_greenpak4.cc | 2 +- 3 files changed, 8 insertions(+), 7 deletions(-) diff --git a/passes/techmap/extract_counter.cc b/passes/techmap/extract_counter.cc index c3e7e9400..6b4ea13e2 100644 --- a/passes/techmap/extract_counter.cc +++ b/passes/techmap/extract_counter.cc @@ -385,7 +385,7 @@ void counter_worker( } //Get new cell name - string countname = string("$auto$COUNTx$") + log_id(extract.rwire->name.str()); + string countname = string("$COUNTx$") + log_id(extract.rwire->name.str()); //Log it total_counters ++; @@ -484,6 +484,7 @@ struct ExtractCounterPass : public Pass { log("\n"); log(" -maxwidth N\n"); log(" Only extract counters up to N bits wide\n"); + log("\n"); log(" -pout X,Y,...\n"); log(" Only allow parallel output from the counter to the listed cell types\n"); log(" (if not specified, parallel outputs are not restricted)\n"); @@ -513,13 +514,13 @@ struct ExtractCounterPass : public Pass { { if(pouts[i] == ',') { - parallel_cells.insert(RTLIL::IdString(tmp)); + parallel_cells.insert(RTLIL::escape_id(tmp)); tmp = ""; } else tmp += pouts[i]; } - parallel_cells.insert(RTLIL::IdString(tmp)); + parallel_cells.insert(RTLIL::escape_id(tmp)); continue; } diff --git a/techlibs/greenpak4/cells_map.v b/techlibs/greenpak4/cells_map.v index 1450eac2e..b0ec9fd3e 100644 --- a/techlibs/greenpak4/cells_map.v +++ b/techlibs/greenpak4/cells_map.v @@ -164,7 +164,7 @@ module \$__COUNT_ (CE, CLK, OUT, POUT, RST, UP); //If we have a CE, or DIRECTION other than DOWN fail... GP_COUNTx_ADV is not supported yet if(HAS_CE || (DIRECTION != "DOWN") ) begin initial begin - $display("ERROR: \$__COUNT__ support for GP_COUNTx_ADV is not yet implemented. This counter should never have been extracted (bug in extract_counter pass?)."); + $display("ERROR: \$__COUNT_ support for GP_COUNTx_ADV is not yet implemented. This counter should never have been extracted (bug in extract_counter pass?)."); $finish; end end @@ -172,7 +172,7 @@ module \$__COUNT_ (CE, CLK, OUT, POUT, RST, UP); //If counter is more than 14 bits wide, complain (also shouldn't happen) else if(WIDTH > 14) begin initial begin - $display("ERROR: \$__COUNT__ support for cascaded counters is not yet implemented. This counter should never have been extracted (bug in extract_counter pass?)."); + $display("ERROR: \$__COUNT_ support for cascaded counters is not yet implemented. This counter should never have been extracted (bug in extract_counter pass?)."); $finish; end end @@ -180,7 +180,7 @@ module \$__COUNT_ (CE, CLK, OUT, POUT, RST, UP); //If counter is more than 8 bits wide and has parallel output, we have a problem else if(WIDTH > 8 && HAS_POUT) begin initial begin - $display("ERROR: \$__COUNT__ support for 9-14 bit counters with parallel output is not yet implemented. This counter should never have been extracted (bug in extract_counter pass?)."); + $display("ERROR: \$__COUNT_ support for 9-14 bit counters with parallel output is not yet implemented. This counter should never have been extracted (bug in extract_counter pass?)."); $finish; end end diff --git a/techlibs/greenpak4/synth_greenpak4.cc b/techlibs/greenpak4/synth_greenpak4.cc index 56ea8003e..5e0e9e5d5 100644 --- a/techlibs/greenpak4/synth_greenpak4.cc +++ b/techlibs/greenpak4/synth_greenpak4.cc @@ -155,7 +155,7 @@ struct SynthGreenPAK4Pass : public ScriptPass if (check_label("fine")) { - run("extract_counter -pout \\GP_DCMP,\\GP_DAC -maxwidth 14"); + run("extract_counter -pout GP_DCMP,GP_DAC -maxwidth 14"); run("clean"); run("opt -fast -mux_undef -undriven -fine"); run("memory_map"); From ed1e3ed39bf15ff9276587325920a329321bdac2 Mon Sep 17 00:00:00 2001 From: Andrew Zonenberg Date: Wed, 30 Aug 2017 18:14:22 -0700 Subject: [PATCH 5/5] extract_counter: Added optimizations to remove unused high-order bits --- passes/techmap/extract_counter.cc | 50 +++++++++++++++++++++---------- 1 file changed, 34 insertions(+), 16 deletions(-) diff --git a/passes/techmap/extract_counter.cc b/passes/techmap/extract_counter.cc index 6b4ea13e2..540b1593d 100644 --- a/passes/techmap/extract_counter.cc +++ b/passes/techmap/extract_counter.cc @@ -387,22 +387,6 @@ void counter_worker( //Get new cell name string countname = string("$COUNTx$") + log_id(extract.rwire->name.str()); - //Log it - total_counters ++; - string reset_type = "non-resettable"; - if(extract.has_reset) - { - //TODO: support other kind of reset - reset_type = "async resettable"; - } - log(" Found %d-bit %s down counter %s (counting from %d) for register %s declared at %s\n", - extract.width, - reset_type.c_str(), - countname.c_str(), - extract.count_value, - log_id(extract.rwire->name), - count_reg_src.c_str()); - //Wipe all of the old connections to the ALU cell->unsetPort("\\A"); cell->unsetPort("\\B"); @@ -466,6 +450,40 @@ void counter_worker( cells_to_remove.insert(extract.count_reg); cells_to_remove.insert(extract.underflow_inv); + //Log it + total_counters ++; + string reset_type = "non-resettable"; + if(extract.has_reset) + { + //TODO: support other kind of reset + reset_type = "async resettable"; + } + log(" Found %d-bit %s down counter %s (counting from %d) for register %s declared at %s\n", + extract.width, + reset_type.c_str(), + countname.c_str(), + extract.count_value, + log_id(extract.rwire->name), + count_reg_src.c_str()); + + //Optimize the counter + //If we have no parallel output, and we have redundant bits, shrink us + if(extract.pouts.empty()) + { + //TODO: Need to update this when we add support for counters with nonzero reset values + //to make sure the reset value fits in our bit space too + + //Optimize it + int newbits = ceil(log2(extract.count_value)); + if(extract.width != newbits) + { + cell->setParam("\\WIDTH", RTLIL::Const(newbits)); + log(" Optimizing out %d unused high-order bits (new width is %d)\n", + extract.width - newbits, + newbits); + } + } + //Finally, rename the cell cells_to_rename.insert(pair(cell, countname)); }