mirror of https://github.com/YosysHQ/yosys.git
Minor bugfix in submod
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617693e691
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1827a48964
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@ -169,6 +169,7 @@ struct SubmodWorker
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}
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}
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new_mod->fixup_ports();
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new_mod->fixup_ports();
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ct.setup_module(new_mod);
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for (RTLIL::Cell *cell : submod.cells) {
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for (RTLIL::Cell *cell : submod.cells) {
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RTLIL::Cell *new_cell = new_mod->addCell(cell->name, cell);
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RTLIL::Cell *new_cell = new_mod->addCell(cell->name, cell);
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