mirror of https://github.com/YosysHQ/yosys.git
Use default copy constructor for RTLIL::SigBit
There was a handwritten copy constructor, which I'm not sure was actually legal C++ (it unconditionally read from the 'data' member of a union, which wouldn't have been written if wire was true). It was also a bit less efficient than the constructor you get from the compiler by default (which is allowed to just copy the memory). This gives a marginal (~0.25%) decrease in code size when compiled with GCC 9.3.
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@ -721,7 +721,7 @@ struct RTLIL::SigBit
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SigBit(const RTLIL::SigChunk &chunk);
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SigBit(const RTLIL::SigChunk &chunk);
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SigBit(const RTLIL::SigChunk &chunk, int index);
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SigBit(const RTLIL::SigChunk &chunk, int index);
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SigBit(const RTLIL::SigSpec &sig);
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SigBit(const RTLIL::SigSpec &sig);
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SigBit(const RTLIL::SigBit &sigbit);
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SigBit(const RTLIL::SigBit &sigbit) = default;
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RTLIL::SigBit &operator =(const RTLIL::SigBit &other) = default;
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RTLIL::SigBit &operator =(const RTLIL::SigBit &other) = default;
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bool operator <(const RTLIL::SigBit &other) const;
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bool operator <(const RTLIL::SigBit &other) const;
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@ -1494,7 +1494,6 @@ inline RTLIL::SigBit::SigBit(RTLIL::Wire *wire) : wire(wire), offset(0) { log_as
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inline RTLIL::SigBit::SigBit(RTLIL::Wire *wire, int offset) : wire(wire), offset(offset) { log_assert(wire != nullptr); }
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inline RTLIL::SigBit::SigBit(RTLIL::Wire *wire, int offset) : wire(wire), offset(offset) { log_assert(wire != nullptr); }
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inline RTLIL::SigBit::SigBit(const RTLIL::SigChunk &chunk) : wire(chunk.wire) { log_assert(chunk.width == 1); if (wire) offset = chunk.offset; else data = chunk.data[0]; }
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inline RTLIL::SigBit::SigBit(const RTLIL::SigChunk &chunk) : wire(chunk.wire) { log_assert(chunk.width == 1); if (wire) offset = chunk.offset; else data = chunk.data[0]; }
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inline RTLIL::SigBit::SigBit(const RTLIL::SigChunk &chunk, int index) : wire(chunk.wire) { if (wire) offset = chunk.offset + index; else data = chunk.data[index]; }
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inline RTLIL::SigBit::SigBit(const RTLIL::SigChunk &chunk, int index) : wire(chunk.wire) { if (wire) offset = chunk.offset + index; else data = chunk.data[index]; }
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inline RTLIL::SigBit::SigBit(const RTLIL::SigBit &sigbit) : wire(sigbit.wire), data(sigbit.data){ if (wire) offset = sigbit.offset; }
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inline bool RTLIL::SigBit::operator<(const RTLIL::SigBit &other) const {
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inline bool RTLIL::SigBit::operator<(const RTLIL::SigBit &other) const {
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if (wire == other.wire)
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if (wire == other.wire)
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