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Merge pull request #1684 from YosysHQ/eddie/xilinx_arith_map 

Fix/cleanup +/xilinx/arith_map.v
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Eddie Hung 2020-02-06 13:51:23 -08:00 committed by GitHub
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1 changed files with 43 additions and 109 deletions
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techlibs/xilinx/arith_map.v
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@ -53,63 +53,31 @@ module _80_xilinx_lcu (P, G, CI, CO);
localparam MAX_WIDTH = CARRY4_COUNT * 4; localparam MAX_WIDTH = CARRY4_COUNT * 4;
localparam PAD_WIDTH = MAX_WIDTH - WIDTH; localparam PAD_WIDTH = MAX_WIDTH - WIDTH;
wire [MAX_WIDTH-1:0] S = {{PAD_WIDTH{1'b0}}, P & ~G}; wire [MAX_WIDTH-1:0] S = {{PAD_WIDTH{1'b0}}, P & ~G};
wire [MAX_WIDTH-1:0] C = CO; wire [MAX_WIDTH-1:0] GG = {{PAD_WIDTH{1'b0}}, G};
wire [MAX_WIDTH-1:0] C;
assign CO = C;
generate for (i = 0; i < CARRY4_COUNT; i = i + 1) begin:slice generate for (i = 0; i < CARRY4_COUNT; i = i + 1) begin:slice
if (i == 0) begin
// Partially occupied CARRY4 CARRY4 carry4
if ((i+1)*4 > WIDTH) begin (
.CYINIT(CI),
// First one .CI (1'd0),
if (i == 0) begin .DI (GG[i*4 +: 4]),
CARRY4 carry4_1st_part .S (S [i*4 +: 4]),
( .CO (C [i*4 +: 4]),
.CYINIT(CI), );
.CI (1'd0),
.DI (G [(WIDTH - 1):i*4]),
.S (S [(WIDTH - 1):i*4]),
.CO (CO[(WIDTH - 1):i*4]),
);
// Another one
end else begin
CARRY4 carry4_part
(
.CYINIT(1'd0),
.CI (C [i*4 - 1]),
.DI (G [(WIDTH - 1):i*4]),
.S (S [(WIDTH - 1):i*4]),
.CO (CO[(WIDTH - 1):i*4]),
);
end
// Fully occupied CARRY4
end else begin end else begin
CARRY4 carry4
// First one (
if (i == 0) begin .CYINIT(1'd0),
CARRY4 carry4_1st_full .CI (C [i*4 - 1]),
( .DI (GG[i*4 +: 4]),
.CYINIT(CI), .S (S [i*4 +: 4]),
.CI (1'd0), .CO (C [i*4 +: 4]),
.DI (G [((i+1)*4 - 1):i*4]), );
.S (S [((i+1)*4 - 1):i*4]),
.CO (CO[((i+1)*4 - 1):i*4]),
);
// Another one
end else begin
CARRY4 carry4_full
(
.CYINIT(1'd0),
.CI (C [i*4 - 1]),
.DI (G [((i+1)*4 - 1):i*4]),
.S (S [((i+1)*4 - 1):i*4]),
.CO (CO[((i+1)*4 - 1):i*4]),
);
end
end end
end endgenerate end endgenerate
`endif `endif
@ -254,67 +222,33 @@ module _80_xilinx_alu (A, B, CI, BI, X, Y, CO);
wire [MAX_WIDTH-1:0] S = {{PAD_WIDTH{1'b0}}, AA ^ BB}; wire [MAX_WIDTH-1:0] S = {{PAD_WIDTH{1'b0}}, AA ^ BB};
wire [MAX_WIDTH-1:0] DI = {{PAD_WIDTH{1'b0}}, AA & BB}; wire [MAX_WIDTH-1:0] DI = {{PAD_WIDTH{1'b0}}, AA & BB};
wire [MAX_WIDTH-1:0] C = CO; wire [MAX_WIDTH-1:0] O;
wire [MAX_WIDTH-1:0] C;
assign Y = O, CO = C;
genvar i; genvar i;
generate for (i = 0; i < CARRY4_COUNT; i = i + 1) begin:slice generate for (i = 0; i < CARRY4_COUNT; i = i + 1) begin:slice
if (i == 0) begin
// Partially occupied CARRY4 CARRY4 carry4
if ((i+1)*4 > Y_WIDTH) begin (
.CYINIT(CI),
// First one .CI (1'd0),
if (i == 0) begin .DI (DI[i*4 +: 4]),
CARRY4 carry4_1st_part .S (S [i*4 +: 4]),
( .O (O [i*4 +: 4]),
.CYINIT(CI), .CO (C [i*4 +: 4])
.CI (1'd0), );
.DI (DI[(Y_WIDTH - 1):i*4]),
.S (S [(Y_WIDTH - 1):i*4]),
.O (Y [(Y_WIDTH - 1):i*4]),
.CO (CO[(Y_WIDTH - 1):i*4])
);
// Another one
end else begin
CARRY4 carry4_part
(
.CYINIT(1'd0),
.CI (C [i*4 - 1]),
.DI (DI[(Y_WIDTH - 1):i*4]),
.S (S [(Y_WIDTH - 1):i*4]),
.O (Y [(Y_WIDTH - 1):i*4]),
.CO (CO[(Y_WIDTH - 1):i*4])
);
end
// Fully occupied CARRY4
end else begin end else begin
CARRY4 carry4
// First one (
if (i == 0) begin .CYINIT(1'd0),
CARRY4 carry4_1st_full .CI (C [i*4 - 1]),
( .DI (DI[i*4 +: 4]),
.CYINIT(CI), .S (S [i*4 +: 4]),
.CI (1'd0), .O (O [i*4 +: 4]),
.DI (DI[((i+1)*4 - 1):i*4]), .CO (C [i*4 +: 4])
.S (S [((i+1)*4 - 1):i*4]), );
.O (Y [((i+1)*4 - 1):i*4]),
.CO (CO[((i+1)*4 - 1):i*4])
);
// Another one
end else begin
CARRY4 carry4_full
(
.CYINIT(1'd0),
.CI (C [i*4 - 1]),
.DI (DI[((i+1)*4 - 1):i*4]),
.S (S [((i+1)*4 - 1):i*4]),
.O (Y [((i+1)*4 - 1):i*4]),
.CO (CO[((i+1)*4 - 1):i*4])
);
end
end end
end endgenerate end endgenerate
`endif `endif