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Merge pull request #550 from jimparis/yosys-upstream 

Support SystemVerilog `` extension for macros
This commit is contained in:
Clifford Wolf 2018-05-17 14:10:24 +02:00 committed by GitHub
parent c3be94e967 4a229e5b95
commit 177a989e48
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1 changed files with 6 additions and 1 deletions
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7
frontends/verilog/preproc.cc
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@ -183,8 +183,9 @@ static std::string next_token(bool pass_newline = false)
const char *ok = "abcdefghijklmnopqrstuvwxyz_ABCDEFGHIJKLMNOPQRSTUVWXYZ$0123456789";
if (ch == '`' || strchr(ok, ch) != NULL)
{
char first = ch;
ch = next_char();
if (ch == '"') {
if (first == '`' && (ch == '"' || ch == '`')) {
token += ch;
} else do {
if (strchr(ok, ch) == NULL) {
@ -244,6 +245,7 @@ static bool try_expand_macro(std::set<std::string> &defines_with_args,
args.push_back(std::string());
while (1)
{
skip_spaces();
tok = next_token(true);
if (tok == ")" || tok == "}" || tok == "]")
level--;
@ -264,6 +266,9 @@ static bool try_expand_macro(std::set<std::string> &defines_with_args,
}
insert_input(defines_map[name]);
return true;
} else if (tok == "``") {
// Swallow `` in macro expansion
return true;
} else return false;
}