mirror of https://github.com/YosysHQ/yosys.git
memory_bram: Make use of new mem emulation functions to map more RAMs.
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5e4c6915c9
commit
1759c80a3f
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@ -644,22 +644,6 @@ grow_read_ports:;
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log(" Bram port %c%d.%d has incompatible clock polarity.\n", pi.group + 'A', pi.index + 1, pi.dupidx + 1);
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goto skip_bram_rport;
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}
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if (port.en != State::S1 && pi.enable == 0) {
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log(" Bram port %c%d.%d has no read enable input.\n", pi.group + 'A', pi.index + 1, pi.dupidx + 1);
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goto skip_bram_rport;
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}
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if (port.arst != State::S0) {
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log(" Bram port %c%d.%d has no async reset input.\n", pi.group + 'A', pi.index + 1, pi.dupidx + 1);
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goto skip_bram_rport;
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}
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if (port.srst != State::S0) {
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log(" Bram port %c%d.%d has no sync reset input.\n", pi.group + 'A', pi.index + 1, pi.dupidx + 1);
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goto skip_bram_rport;
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}
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if (!port.init_value.is_fully_undef()) {
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log(" Bram port %c%d.%d has no initial value support.\n", pi.group + 'A', pi.index + 1, pi.dupidx + 1);
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goto skip_bram_rport;
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}
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if (non_transp && read_transp.count(pi.transp) && read_transp.at(pi.transp)) {
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log(" Bram port %c%d.%d has incompatible read transparency.\n", pi.group + 'A', pi.index + 1, pi.dupidx + 1);
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goto skip_bram_rport;
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@ -794,10 +778,18 @@ grow_read_ports:;
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// Apply make_outreg and make_transp where necessary.
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for (auto &pi : portinfos) {
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if (pi.make_outreg)
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mem.extract_rdff(pi.mapped_port, initvals);
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if (pi.make_transp) {
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if (pi.mapped_port == -1 || pi.wrmode)
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continue;
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auto &port = mem.rd_ports[pi.mapped_port];
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if (pi.make_outreg) {
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mem.extract_rdff(pi.mapped_port, initvals);
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} else if (port.clk_enable) {
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if (!pi.enable && port.en != State::S1)
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mem.emulate_rden(pi.mapped_port, initvals);
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else
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mem.emulate_reset(pi.mapped_port, true, true, true, initvals);
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}
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if (pi.make_transp) {
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for (int i = 0; i < GetSize(mem.wr_ports); i++)
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if (port.transparency_mask[i])
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mem.emulate_transparency(i, pi.mapped_port, initvals);
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