Merge pull request #975 from YosysHQ/clifford/fix968

Re-enable "final loop assignment" feature and fix opt_clean warnings

frontends/ast/simplify.cc

@@ -1172,14 +1172,12 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 			varbuf->children[0] = buf;
 		}
 
-#if 0
 		if (type == AST_FOR) {
 			AstNode *buf = next_ast->clone();
 			delete buf->children[1];
 			buf->children[1] = varbuf->children[0]->clone();
 			current_block->children.insert(current_block->children.begin() + current_block_idx++, buf);
 		}
-#endif
 
 		current_scope[varbuf->str] = backup_scope_varbuf;
 		delete varbuf;

passes/opt/opt_clean.cc

@@ -85,22 +85,34 @@ void rmunused_module_cells(Module *module, bool verbose)
 {
 	SigMap sigmap(module);
 	pool<Cell*> queue, unused;
+	pool<SigBit> used_raw_bits;
 	dict<SigBit, pool<Cell*>> wire2driver;
+	dict<SigBit, vector<string>> driver_driver_logs;
+
+	SigMap raw_sigmap;
+	for (auto &it : module->connections_) {
+		for (int i = 0; i < GetSize(it.second); i++) {
+			if (it.second[i].wire != nullptr)
+				raw_sigmap.add(it.first[i], it.second[i]);
+		}
+	}
 
 	for (auto &it : module->cells_) {
 		Cell *cell = it.second;
 		for (auto &it2 : cell->connections()) {
-			if (!ct_all.cell_known(cell->type) || ct_all.cell_output(cell->type, it2.first))
+			if (ct_all.cell_known(cell->type) && !ct_all.cell_output(cell->type, it2.first))
-				for (auto raw_bit : it2.second) {
+				continue;
-					if (raw_bit.wire == nullptr)
+			for (auto raw_bit : it2.second) {
-						continue;
+				if (raw_bit.wire == nullptr)
-					auto bit = sigmap(raw_bit);
+					continue;
-					if (bit.wire == nullptr)
+				auto bit = sigmap(raw_bit);
-						log_warning("Driver-driver conflict for %s between cell %s.%s and constant %s in %s: Resolved using constant.\n",
+				if (bit.wire == nullptr)
-								log_signal(raw_bit), log_id(cell), log_id(it2.first), log_signal(bit), log_id(module));
+					driver_driver_logs[raw_sigmap(raw_bit)].push_back(stringf("Driver-driver conflict "
-					if (bit.wire != nullptr)
+							"for %s between cell %s.%s and constant %s in %s: Resolved using constant.",
-						wire2driver[bit].insert(cell);
+							log_signal(raw_bit), log_id(cell), log_id(it2.first), log_signal(bit), log_id(module)));
-				}
+				if (bit.wire != nullptr)
+					wire2driver[bit].insert(cell);
+			}
 		}
 		if (keep_cache.query(cell))
 			queue.insert(cell);
@@ -114,6 +126,8 @@ void rmunused_module_cells(Module *module, bool verbose)
 			for (auto bit : sigmap(wire))
 			for (auto c : wire2driver[bit])
 				queue.insert(c), unused.erase(c);
+			for (auto raw_bit : SigSpec(wire))
+				used_raw_bits.insert(raw_sigmap(raw_bit));
 		}
 	}
 
@@ -142,6 +156,22 @@ void rmunused_module_cells(Module *module, bool verbose)
 		module->remove(cell);
 		count_rm_cells++;
 	}
+
+	for (auto &it : module->cells_) {
+		Cell *cell = it.second;
+		for (auto &it2 : cell->connections()) {
+			if (ct_all.cell_known(cell->type) && !ct_all.cell_input(cell->type, it2.first))
+				continue;
+			for (auto raw_bit : raw_sigmap(it2.second))
+				used_raw_bits.insert(raw_bit);
+		}
+	}
+
+	for (auto it : driver_driver_logs) {
+		if (used_raw_bits.count(it.first))
+			for (auto msg : it.second)
+				log_warning("%s\n", msg.c_str());
+	}
 }
 
 int count_nontrivial_wire_attrs(RTLIL::Wire *w)

tests/simple/forloops.v

@@ -0,0 +1,25 @@
+module forloops01 (input clk, a, b, output reg [3:0] p, q, x, y);
+	integer k;
+	always @(posedge clk) begin
+		for (k=0; k<2; k=k+1)
+			p[2*k +: 2] = {a, b} ^ {2{k}};
+		x <= k + {a, b};
+	end
+	always @* begin
+		for (k=0; k<4; k=k+1)
+			q[k] = {~a, ~b, a, b} >> k[1:0];
+		y = k - {a, b};
+	end
+endmodule
+
+module forloops02 (input clk, a, b, output reg [3:0] q, x, output [3:0] y);
+	integer k;
+	always @* begin
+		for (k=0; k<4; k=k+1)
+			q[k] = {~a, ~b, a, b} >> k[1:0];
+	end
+	always @* begin
+		x = k + {a, b};
+	end
+	assign y = k - {a, b};
+endmodule