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Merge pull request #2326 from YosysHQ/mwk/peeopt-muldiv-sign 

peepopt.muldiv: Add a signedness check.
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clairexen 2020-08-20 16:19:37 +02:00 committed by GitHub
parent 1cdb533fa5 e89cc9c02f
commit 16bb3fc8bb
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GPG Key ID: 4AEE18F83AFDEB23
2 changed files with 16 additions and 1 deletions
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5
passes/pmgen/peepopt_muldiv.pmg
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@ -1,16 +1,18 @@
pattern muldiv pattern muldiv
state <SigSpec> t x y state <SigSpec> t x y
state <bool> is_signed
match mul match mul
select mul->type == $mul select mul->type == $mul
select GetSize(port(mul, \A)) + GetSize(port(mul, \B)) <= GetSize(port(mul, \Y)) select GetSize(port(mul, \A)) + GetSize(port(mul, \B)) <= GetSize(port(mul, \Y))
endmatch endmatch
code t x y code t x y is_signed
t = port(mul, \Y); t = port(mul, \Y);
x = port(mul, \A); x = port(mul, \A);
y = port(mul, \B); y = port(mul, \B);
is_signed = param(mul, \A_SIGNED).as_bool();
branch; branch;
std::swap(x, y); std::swap(x, y);
endcode endcode
@ -19,6 +21,7 @@ match div
select div->type.in($div) select div->type.in($div)
index <SigSpec> port(div, \A) === t index <SigSpec> port(div, \A) === t
index <SigSpec> port(div, \B) === x index <SigSpec> port(div, \B) === x
filter param(div, \A_SIGNED).as_bool() == is_signed
endmatch endmatch
code code

12
tests/opt/bug2318.ys Normal file
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@ -0,0 +1,12 @@
read_verilog <<EOT
module t(input [3:0] A, input [3:0] B, output signed [3:0] Y);
wire [7:0] P = A * B;
wire signed [7:0] SP = P;
wire signed [3:0] SB = B;
assign Y = SP / SB;
endmodule
EOT
equiv_opt -assert peepopt