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Merge branch 'vector_fix' of https://github.com/Kmanfi/yosys 

Also some minor fixes to the original PR.
This commit is contained in:
Claire Wolf 2020-01-29 17:01:24 +01:00
parent 4d0118d0c1 e558b3284b
commit 1679682fa3
1 changed files with 3 additions and 1 deletions
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4
passes/opt/opt_reduce.cc
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@ -44,9 +44,10 @@ struct OptReduceWorker
cells.erase(cell); cells.erase(cell);
RTLIL::SigSpec sig_a = assign_map(cell->getPort(ID::A)); RTLIL::SigSpec sig_a = assign_map(cell->getPort(ID::A));
sig_a.sort_and_unify();
pool<RTLIL::SigBit> new_sig_a_bits; pool<RTLIL::SigBit> new_sig_a_bits;
for (auto &bit : sig_a.to_sigbit_set()) for (auto &bit : sig_a)
{ {
if (bit == RTLIL::State::S0) { if (bit == RTLIL::State::S0) {
if (cell->type == ID($reduce_and)) { if (cell->type == ID($reduce_and)) {
@ -86,6 +87,7 @@ struct OptReduceWorker
} }
RTLIL::SigSpec new_sig_a(new_sig_a_bits); RTLIL::SigSpec new_sig_a(new_sig_a_bits);
new_sig_a.sort_and_unify();
if (new_sig_a != sig_a || sig_a.size() != cell->getPort(ID::A).size()) { if (new_sig_a != sig_a || sig_a.size() != cell->getPort(ID::A).size()) {
log(" New input vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_a)); log(" New input vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_a));